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The purpose of this paper is to present a selective wet‐etching method of boron doped low‐pressure chemical vapour deposition (LPCVD) polysilicon film for the realization of piezoresistors over the bulk micromachined diaphragm of (100) silicon with improved yield and uniformity.

The method introduces discretization of the LPCVD polysilicon film using prior etching for the grid thus dividing each chip on the entire wafer. The selective etching of polysilicon for realizing of piezoresistors is limited to each chip area with individual boundaries.

The method provides a uniform etching on the entire silicon wafer irrespective of its size and leads to economize the fabrication process in a batch production environment with improved yield.

The method introduces one extra process step of photolithography and subsequent etching for discretizing the polysilicon film.

The method is useful to enhance yield while defining metal lines for contact purposes on fabricated electronic structures using microelectronics. Stress developed in LPCVD polysilicon can be removed using proposed approach of discretization of polysilicon film.

The work is an outcome of regular fabrication work using conventional approaches in an R&D environment. The proposed method replaces the costly reactive ion etching techniques with stable reproducibility and ease in its implementation.

As the feature sizes of microelectronic and optoelectronic components continue to decrease, there has been increased interest in developing new techniques for etching the materials used to construct these highly integrated components. Features of the new techniques now being investigated include etching with neutral species, maskless processing, material selectivity, and reduced electrical damage.

The purpose of this paper is to synthesize porous zinc oxide (ZnO) by means of strain etching/wet chemical etching method with the use of 0.5% of nitric acid (HNO₃) etchant. The structural and surface morphological properties of the samples are accessed by using X‐ray diffraction (XRD) and scanning electron microscopy (SEM) characterization techniques.

ZnO samples used in this work were deposited on the p‐Si (111) substrates by using radio frequency (RF) sputtering technique. Wet chemical etching processes with the use of 0.5% HNO₃ etchant was applied on these samples in order to obtain porous structure. The porous ZnO samples are characterized by means of XRD and SEM to access their structural and surface morphological properties.

The XRD and SEM cross‐sectional measurements revealed that the thickness of the etched ZnO thin films is proportional to the etching time. SEM micrographs show that the surface morphology of ZnO changes over etching time. On the other hand, XRD results indicate that the crystallite sizes of the ZnO(002) decreases when the etching time increases.

The paper shows how porous ZnO thin films have been successfully synthesized by using simple wet chemical etching. SEM images reveal that this method is reliable when producing porous structure ZnO surfaces.

This paper aims to develop an ideal technique for the preparation of print circuit boards (PCBs) with ladder conductive lines on practical industrial process lines.

First, the raw materials of ladder copper-clad laminates were prepared by plating double-sided copper-clad laminates with vertical plating line. Second, etching compensation experiments were designed and conducted to set up the relationships between etching compensation and width of conductive lines on ladder line print circuit boards (LLPCBs). Third, to evaluate the process technique for the preparation of LLPCBs through etching compensation, verification experiments were designed and conducted on a practical industrial process line, and the quality of lines on LLPCBs was observed and evaluated.

Under the judgment of the quality of conductive lines on LLPCBs as well as the feasibility with a practical industrial process line, the process technique for the preparation of LLPCBs with etching compensation is a simple and reliable method which has the potential to be applied in the industry.

It is the first successful report of a new method that produces LLPCBs with etching compensation and has the potential to be applied in the industry.

Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best.

Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp.

Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality.

Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.

The purpose of this paper is to study an electrolytic etching method to prepare fine lines on printed circuit board (PCB). And the influence of organics on the side corrosion protection of PCB fine lines during electrolytic etching is studied in detail.

In this paper, the etching factor of PCB fine lines produced by new method and the traditional method was analyzed by the metallographic microscope. In addition, field emission scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to study the inhibition of undercut of the four organometallic corrosion inhibitors with 2,5-dimercapto-1,3,4-thiadiazole, benzotriazole, l-phenylalanine and l-tryptophan in the electrolytic etching process.

The SEM results show that corrosion inhibitors can greatly inhibit undercut of PCB fine lines during electrolytic etching process. XPS results indicate that N and S atoms on corrosion inhibitors can form covalent bonds with copper during electrolytic etching process, which can be adsorbed on sidewall of PCB fine lines to form a dense protective film, thereby inhibiting undercut of PCB fine lines. Quantum chemical calculations show that four corrosion inhibitor molecules tend to be parallel to copper surface and adsorb on copper surface in an optimal form. COMSOL Multiphysics simulation revealed that there is a significant difference in the amount of corrosion inhibitor adsorbed on sidewall of the fine line and the etching area.

As a clean production technology, electrolytic etching method has a good development indicator for the production of high-quality fine lines in PCB industry in the future. And it is of great significance in saving resources and reducing environmental pollution.

The subtractive method is widely used to produce high‐density PWBs. It is generally accepted that a pattern pitch of 100 microns or less cannot be achieved by the subtractive method because of the thickness of the copper layer to be etched. We report here on experiments to investigate the relationship between the pattern pitch of a circuit formed by the subtractive method and the required thickness of the copper layer. We have also determined the allowable thickness of the copper layer, plating layer, and copper foil layer for achieving a pattern pitch of 100 microns (L/S = 50/50 microns) or less.

The purpose of this paper is to investigate the morphology of intermetallic (IMC) compounds and the mechanical properties of SAC305 solder alloy under different cooling conditions.

SAC305 solder joints were prepared under different cooling conditions/rates. The performance of three different etching methods was investigated: simple chemical etching, deep etching based on the Jackson method and selective removal of β-Sn by a standard three-electrode cell method. Phase and structural analyses were conducted by X-ray diffraction (XRD). The morphology of etched solder was examined by a field emission scanning electron microscope. The hardness evaluations of the solder joints were conducted by a Vickers microhardness tester.

The Ag₃Sn network was significantly refined by the ice-quenching process. Further, the thickness of the Cu₆Sn₅ layer decreased with an increase in the cooling rate. The finer Ag₃Sn network and the thinner Cu₆Sn₅ IMC layer were the results of the reduced solidification time. The ice-quenched solder joints showed the highest hardness values because of the refinement of the Ag₃Sn and Cu₆Sn₅ phases.

The reduction in the XRD peak intensities showed the influence of the cooling condition on the formation of the different phases. The micrographs prepared by electrochemical etching revealed better observations regarding the shape and texture of the IMC phases than those prepared by the conventional etching method. The lower grain orientation sensitivity of the electrochemical etching method (unlike chemical etching) significantly improved the micrographs and enabled accurate observation of IMC phases.

The purpose of this paper is to introduce trench termination for high power buried‐gate static induction transistor (SIT) comprising three parts, which can inhibit the reverse leakage current substantially and paradisaical current. The simplified step‐etching process will also be discussed in detail.

For power buried‐gate SIT, the trench termination comprises three grooves, gate electrode etching, mesa‐groove etching and the separated groove, respectively. The simplified step‐etching process is proposed to optimize the traditional technical processing.

The tripartite trench termination of power SIT can inhibit the reverse leakage current, improve the gate‐source breakdown and increase the blocking voltage. The step‐etching process which is proposed for the first time, realizes the tripartite trench termination simultaneously which simplifies the traditional processes and is beneficial by protecting the surface of the die. The optimum etched depth of termination is also presented with experimentations.

The tripartite trench termination of power SIT is novel and the step‐etching process is also proposed for the first time.

To fabricate submicrometer thin membrane of silicon nitride and silicon dioxide over an anisotropically etched cavity in (100) silicon.

PECVD of silicon dioxide and Silcion nitride layers of compatible thicknesses followed by thermal annealing in nitrogen ambients at 1,000°C for 30 min, leads to stable membrane formation. Anisotropic etching of (100) silicon below the membrane through channels on the sides has been used with controlled cavity dimensions.

Lateral front side etching through channels slows down etching rate drastically. The etching mechanism has been discussed with experimental details.

Vacuum sealed cavity membranes can be realised for micro sensor applications.

The process is new and feasible for micro sensor technologies.