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Widely accepted classifications of benchmarking distinguish between different levels of benchmarking. Strategic‐level benchmarking is considered to be of a higher sophistication than product‐level benchmarking. Such strategic benchmarking would be based on process information instead of product information. The purpose of this paper is to research the possibility of obtaining strategic‐level information based on an extensive amount of product‐level benchmark data.

The data used in this paper originate from the environmental benchmarking program of Philips Consumer Electronics (CE). Philips CE has successfully implemented benchmarking as an environmental improvement strategy for its products. Product‐level competitive benchmarking is used to assess the environmental performance of a Philips' product compared to its main economic rivals. Since the start of environmental benchmarking a considerable pool of product‐level benchmark data has been generated. This paper reports on an extensive data analysis of product‐level benchmarking data concerning the packaging of these consumer electronics products.

It is shown how strategic‐level information is obtained from a data analysis of these separate benchmarking studies, resulting both in useful strategic‐level managerial information and practical design input. Finally, advantages of this approach as compared to classic strategic‐level benchmarking are identified.

The study has yielded empirical data indicating a limitation in current benchmarking classification.

The paper offers insights into the benefits of product level benchmarking for strategic eco‐efficient decision making.

The advent of novel advanced packaging technologies such as multilayer thin‐film interconnect, combined with continuous improvements in IC clock speed and circuit performance, has placed extreme demands on electronics packaging and package materials. Aluminium nitride (AIN) ceramic offers significant opportunities and advantages for package design, particularly where the effective thermal management and overall reliability of large devices are a high priority. AIN has already been successfully employed at the substrate level for the enhanced thermal relief of power devices. Examples of these applications include heat sinks and device mounts for thyristor modules, power transistors, solid state relays, power SCRs, switching modules, LEDs and various RF package configurations. Both bare and metallised AIN substrates are beginning to find application as a substitute for beryllia (BeO) in mass market and high reliability automotive electronics applications. Successfully implementing AIN in a high level electronics packaging application requires a systems approach in which the intrinsic properties of AIN are considered as ‘first principles’ in shaping the package design process. The unique physicochemical and mechanical properties of AIN require the development of specialised metallisation and co‐firing processes to fabricate the advanced components necessary for hermetic packaging of complex devices and multichip modules. This paper presents a practical and mass manufacturable AIN‐based package tailored to these high level applications. The package design is unique in that it provides for the total separation of the electrical‐signal conduction from the mechanical support/mounting functions of the package. Such a separation of the functions improves both the package durability and reliability relative to currently available electronics packages of conventional designs.

The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.

This paper aims to demonstrate the improved functionality of additive manufacturing technology provided by combining multiple processes for the fabrication of packaged electronics.

This research is focused on the improvement in resolution of conductor deposition methods through experimentation with build parameters. Material dispensing with two different low temperature curing isotropic conductive adhesive materials was characterised for their application in printing each of three different conductor designs, traces, z-axis connections and fine pitch flip chip interconnects. Once optimised, demonstrator size can be minimised within the limitations of the chosen processes and materials.

The proposed method of printing z-axis through layer connections was successful with pillars 2 mm in height and 550 µm in width produced. Dispensing characterisation also resulted in tracks 134 µm in width and 38 µm in height allowing surface mount assembly of 0603 components and thin-shrink small outline packaged integrated circuits. Small 149-µm flip chip interconnects deposited at a 457-µm pitch have also been used for packaging silicon bare die.

This paper presents an improved multifunctional additive manufacturing method to produce fully packaged multilayer electronic systems. It discusses the development of new 3D printed, through layer z-axis connections and the use of a single electrically conductive adhesive material to produce all conductors. This facilitates the surface mount assembly of components directly onto these conductors before stereolithography is used to fully package multiple layers of circuitry in a photopolymer.

To characterise the optical performance of organic multi‐mode optical waveguides integrated with printed circuit board (PCB) and to demonstrate the feasibility of 2.5 and 10 Gbps optical interconnection in board‐level, respectively.

This paper provides both qualitative and quantitative approaches for the characterization the wave guide performance, i.e. using loss measurement, optical beam profiling, ethernet verification, and eye‐diagram testing. In addition to wave guide loss measurement, the most significance part of the work reported in this paper is to evaluate optical wave guides with coupled VCSELs, by which a 3 dB coupling design budget can thus be identified. Furthermore, by artificially manipulating coupling conditions, practical concerns of EOPCB integration, including waveguide geometry, VCSEL driving power, alignment tolerance, coupling spacing, etc. are studied.

Thermal stability studies related to PCB lamination processes show the feasibility of organic waveguides integrated to traditional PCB manufacturing. For a direct VCSEL/PD coupling scheme, a 3 dB power budget is experimentally identified. For short reach optical interconnection, 10 Gbps up to 17 cm propagation on PCB can be achieved by using 50×50 μm multi‐mode organic waveguides, where a±25 μm tolerance of optical alignment is compatible to the design rules of PCB.

The value of the paper lies in its systematic approaches to identify the waveguide performance through both qualitative and quantitative indices. The correlation between geometry design, processes, coupling conditions, and optical performance of organic waveguides explored in detail. Not only is a standard eye‐diagram test used to verify the waveguide at 2.5 and 10 Gbps bandwidth, but also a prototype of optical data‐communication on giga‐ethernet is demonstrated for long term stability. Following these analytical methods, readers can understand more about the optical performance of waveguides when designing optical interconnection for high speed electro‐optical integrated PCBs.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

The set of properties required for microwave packaging materials intended for aerospace applications is discussed in relation to the current range of materials that are commercially available. Initiatives are being taken to replace kovar, the established packaging material, with substitutes which are lighter, stiffer and offer superior heat‐sinking. Promising in this regard are new family of beryllium‐beryllia and also silicon‐aluminium (Si‐Al) alloys high in silicon, with ratios of constituents chosen such that they optimally complement gallium arsenide MMIC devices and alumina circuit boards. Both types of material are relatively easy to machine and electroplate. Demonstrator microwave amplifier modules incorporating the Si‐Al alloys have been designed for space applications and have been successfully produced and tested. The manufacturing technology that has been developed for this purpose is described.

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.

During the first half of this year the Association has continued to expand its exhibition programme by increasing its presence at overseas shows. Two DTI sponsored joint venture groups have been formed, one to Nepcon West, the other to Nepcon Beijing. Anaheim saw the biggest UK group for over 10 years, with CEMA taking three separate blocks in different sectors of the show. There is no doubt from the reception we received that CEMA is now firmly established at Nepcon West. We enjoyed tremendous support from both the British Consulate and the British‐American Chamber of Commerce with their President making several visits to the CEMA booth.