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The purpose of this work is to study the capability of heuristic algorithms like genetic algorithm to estimate the electron transport parameters of the Gallium Arsenide (GaAs). Also, the paper provides a simple but complete electron mobility model for the GaAs based on the genetic algorithm that can be suitable for use in simulation, optimization and design of GaAs‐based electronic and optoelectronic devices.

The genetic algorithm as a powerful heuristic optimization technique is used to approximate the electron transport parameters during the model development.

The capability of the model to approximate the electron transport properties of Gallium Arsenide is tested using experimental and Monte Carlo data. Results show that the genetic algorithm based model can provide a reliable estimate of the electron mobility in Gallium Arsenide for a wide range of temperatures, concentrations and electric fields. Based on the obtained results, this paper shows that the genetic algorithm can be a useful tool for the estimation of the transport parameters of semiconductors.

For the first time, the genetic algorithm is used to calculate the electron transport parameters in Gallium Arsenide. A complete electron mobility model for a wide range of temperatures, doping concentrations, compensation ratios and electric fields is developed.

A two‐dimensional numerical computer simulation based on the analysis of the first three moments of the Boltzmann equation, known as the energy‐transport model, has been used to study various two‐dimensional effects on the performance of AlGaAs/GaAs heterostructure field‐effect transistor. The results are presented for half‐micron gate length. The calculation reveals significant electron current contribution coming from the AlGaAs region between the source and gate, contributing to the reduction of access resistance. As the electrons acquire large energies near the drain side edge of the gate, real‐space transfer to the AlGaAs region from the “two‐dimensional” electron gas channel occurs. However, at the drain end, the electron current is confined at the GaAs side of the heterointerface. The result shows insignificant current contribution from regions of depth greater than 0.048 µm into the undoped GaAs bulk. At room temperature, the results indicate transconductance, current gain cutoff frequency and power density about twice that which are calculated for “equivalent” GaAs MESFET, of identical structure and doping level as the heavily‐doped AlGaAs region. These results suggest that HEMT devices have the potential for providing significant sources of power at millimeter‐wave frequencies.

We introduce the drift‐diffusion model with appropriate jump conditions at the junction of the MODFET transistor (AlGaAs/GaAs). We propose a quasi‐variational inequality (QVI) model for this device. We assume that the electron density is bounded and piecewise constant. These hypotheses imply that the Poisson’s equation becomes linear with respect to the electrostatic potential. The QVI model keeps a coupling with the continuity equation. Free boundaries arise in the medium AlGaAs near the Schottky‐gate contact and in the high mobility medium (GaAs) under the effect of the electron affinity discontinuity at the junction. Numerical results of the QVI model show their location versus the applied gate voltage V/up> and the molar fraction X of the Al_XGa_(1‐X)As medium. The inequality seems to be a reasonable simplification of the non‐linear Poisson’s equation.

Poisson’s equation and the electron continuity equation, together with heat flow equation are solved self‐consistently to obtain the lattice temperature profile under non‐isothermal conditions in a power VDMOS transistor. The effect of the variable lattice temperature on the forward characteristics of VDMOSTs is presented, and discussed. The results show that self‐heating in power VDMOSTs has a significant effect. The thermal coupling effects on the forward I—V characteristics are compared and discussed between the power VDMOST and the conventional MOSFET.

An simple model for the simulation of the electrical behaviour of several types of junction controlled field‐effect transistors is proposed. It is based on the calculation of the carrier concentration in the channel by means of a self‐consistent solution of Schrödinger and Poisson's equation in the direction perpendicular to the current flow. Based on the carrier concentration the dc, the small‐signal, and also the noise properties of the devices may be simulated. The calculated characteristics of a sub‐quarter micron gate GaAs MESFET, a δ‐doped GaAs FET and a Velocity Modulation Transistor will be presented and discussed.

The purpose of this study is to present a systematic investigation of the effect of high temperatures on transport characteristics of nitrogen-doped silicon carbide nanowire-based field-effect transistor (SiC-NWFET). The 3C-SiC nanowires can endure high-temperature environments due to their wide bandgap, high thermal conductivity and outstanding physical and chemical properties.

The metal-organic chemical vapor deposition process was used to synthesize in-situ nitrogen-doped SiC nanowires on SiO₂/Si substrate. To fabricate the proposed SiC-NWFET device, the dielectrophoresis method was used to integrate the grown nanowires on the surface of pre-patterned electrodes onto the SiO₂ layer on a highly doped Si substrate. The transport properties of the fabricated device were evaluated at various temperatures ranging from 25°C to 350°C.

The SiC-NWFET device demonstrated an increase in conductance (from 0.43 mS to 1.2 mS) after applying a temperature of 150°C, and then a decrease in conductance (from 1.2 mS to 0.3 mS) with increasing the temperature to 350°C. The increase in conductance can be attributed to the thermionic emission and tunneling mechanisms, while the decrease can be attributed to the phonon scattering. Additionally, the device revealed high electron and hole mobilities, as well as very low resistivity values at both room temperature and high temperatures.

High-temperature transport properties (above 300°C) of 3C-SiC nanowires have not been reported yet. The SiC-NWFET demonstrates a high transconductance, high electron and hole mobilities, very low resistivity, as well as good stability at high temperatures. Therefore, this study could offer solutions not only for high-power but also for low-power circuit and sensing applications in high-temperature environments (∼350°C).

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

This paper aims at building a discharge model for the power cable bellows based on plasma energy deposition and analyzing the discharge ablation problem.

Aiming at the multiphysical mechanism of the discharge ablation process, a multiphysical field model based on plasma energy deposition is established to analyze the discharge characteristics of the power cable bellows. The electrostatic field, plasma characteristics, energy deposition and temperature field are analyzed. The discharge experiment is also carried out for result validation.

The physical mechanism of the bellows ablative effect caused by partial discharge is studied. The results show that the electric field intensity between the aluminum sheath and the buffer layer easily exceeds the pressure resistance value of air breakdown. On the plasma surface of the buffer layer, the electron density is about 4 × 1,019/m³, and the average temperature of electrons is about 3.5 eV. The energy deposition analysis using the Monte Carlo method shows that the electron range in the plasma is very short. The release will complete within 10 nm, and it only takes 0.1 s to increase the maximum temperature of the buffer layer to more than 1,000 K, thus causing various thermal effects.

Its physical process involves the distortion of electric field, formation of plasma, energy deposition of electrons, and abrupt change of temperature field.

In this paper, the 2‐D numerical analysis is used to investigate the electro‐thermal performance of a trench power VDMOS transistor having a much reduced quasi‐saturation effect over the conventional VDMOS structure. Taking into account all the appropriate physical mechanisms, the analysis self‐consistently solves Poisson's equation, the electron continuity equation and the heat flow equation. The results show that the trench structure introduced enables the device to operate at higher current levels due to a favorable change in current density distribution within the device. However, these two effects can increase the self‐heating of the device, decrease the forward current and degrade the thermal stability of the new structure. Nevertheless the new device is still found to provide a higher quasi‐saturation current than the conventional VDMOS device even when thermal effects are taken into account.

Even though copper–tungsten has shown signs of potentials, relatively little is currently known about its appropriateness for photovoltaic application. This paper aims to evaluate the suitability of copper-tungs oxides as photovoltaic absorbers while investigating the consequences of oxygen content variation.

Using profilometry, Hall measurements, Seebeck test and spectrophotometry, grown samples were defined. Samples of 5 standard cubic centimeters per minute (sccm) and 7 sccm exhibited appropriate characteristics and were further tested using personal computer one dimension (PC1D) computational simulation at the system stage. To grow materials with an average thickness below 0.45 µm, magnetron co-sputtering was used. Three sample sets, varied by oxygen flow rate, were made with flow rates of 5sccm, 7sccm and 9sccm, respectively.

Some samples proved to be effective absorbers, using a cadmium telluride device as the criterion of output calculation, with one sample chosen as ideal for each type of flow rate. For the chosen samples, an optimum thickness was also obtained, i. It was discovered that thinner cells, optimal for both groups with 0.6 µm, performed better to than other thicknesses.

The material also demonstrated prospects for applications in window layers, but more needs to be known.

Thin film material properties and their operating processes are relatively complex, so it is important to find simple and cost-effective ways to forecast performance. While relatively new, numerical modeling has proven to be very useful in defining the critical properties of thin film devices, thereby helpful for predictions of performance. Solar cell capacitance simulator one dimension, amorphous semiconductor analysis, personal computer one dimension (PC1D), analysis of micro-electronic and photonic structures and automat for simulation for heterostructures (33) are several common models in the thin film industry. Due to its availability and relative ease of use, PC1D was used in this project.

As the search for the balance among performance, cost, reliability and availability continue, more absorber components continue to evolve, notably from the chalcogenides. Because of their ability to absorb light, ternary transition metal chalcogenides are useful in the production of hydrogen and in the energy storage sector, as well as in the production of light-emitting diodes and solar photovoltaic (PV).

There are several methods for the manufacture of copper–tungsten alloys, but the process of combinatorial sputtering of magnetrons provides satisfactory results even for the manufacture of various other materials. Cu₂WSe₄, an excellent alternative to sputtering, is one of the very few copper–tungsten selenide materials tested, synthesized by hot simple injection to have strong crystallinity and lacks impurity. The optical properties of colloidal Cu₂WSe₄ show that Schottky diode–like behaviors are present in the material, suggesting its potential for use in solar cells. Cu-W alloys could have a lot more to give the PV industry, by all indications. Further exploration of the oxides by this work is thus justified. Transparent conducting oxides, interfacial layers or charge-transporting compounds are commonly used as transition metal oxides. Nevertheless, as absorbers, metal oxides such as BiFeO₃ and the traditionally highly studied Cu₂O have been tested, with Cu₂O showing a conversion efficiency of up to 10% under particular conditions. This displays strong electronic and optical properties, so there might be some possibility of studying other PV absorption metal oxides. The optical properties of colloidal Cu₂WSe₄ show that Schottky diode–like behaviors are present in the material, suggesting its potential for use in solar cells.