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The purpose of this paper is to investigate the morphology of intermetallic (IMC) compounds and the mechanical properties of SAC305 solder alloy under different cooling conditions.

SAC305 solder joints were prepared under different cooling conditions/rates. The performance of three different etching methods was investigated: simple chemical etching, deep etching based on the Jackson method and selective removal of β-Sn by a standard three-electrode cell method. Phase and structural analyses were conducted by X-ray diffraction (XRD). The morphology of etched solder was examined by a field emission scanning electron microscope. The hardness evaluations of the solder joints were conducted by a Vickers microhardness tester.

The Ag₃Sn network was significantly refined by the ice-quenching process. Further, the thickness of the Cu₆Sn₅ layer decreased with an increase in the cooling rate. The finer Ag₃Sn network and the thinner Cu₆Sn₅ IMC layer were the results of the reduced solidification time. The ice-quenched solder joints showed the highest hardness values because of the refinement of the Ag₃Sn and Cu₆Sn₅ phases.

The reduction in the XRD peak intensities showed the influence of the cooling condition on the formation of the different phases. The micrographs prepared by electrochemical etching revealed better observations regarding the shape and texture of the IMC phases than those prepared by the conventional etching method. The lower grain orientation sensitivity of the electrochemical etching method (unlike chemical etching) significantly improved the micrographs and enabled accurate observation of IMC phases.

The purpose of this study is to explore the mechanism of branch pits and tunnels formation and increase the specific surface area and capacitance of anode Al foil for high voltage electrolytic capacitor by D.C. etching in acidic solution and neutral.

Al foil was first D.C. etched in HCl-H₂SO₄ mixed acidic solution to form main tunnels perpendicular to the Al surface, and then D.C. etched in neutral NaCl solution including 0.5 per cent C₆H₈O₇ and Cu(NO₃)₂ with different concentration to form branch tunnels normal to Al surface. Between two etching, Cu nuclei were electroless deposited on the interior surface of main tunnels by natural occluded corrosion cell effect to form micro Cu-Al galvanic local cells. The effects of electroless deposited Cu nuclei on cross-section etching morphologies and electrochemical behavior of Al foil was investigated with SEM, polarization curve and electrochemical impedance spectroscopy (EIS).

The results show that sub branch tunnels can form along the main tunnels owing to the formation of Cu-Al micro-batteries, in which Cu is cathode and Al is anode. With increase in Cu(NO₃)₂ concentration, more Cu nuclei can be electroless deposited and serve as the favorable sites for branch tunnel initiation along the whole length of main tunnels, leading to enhancement in specific capacitance of anode Al foil.

Cu nuclei were electroless deposited on the interior surface of main tunnels by natural occluded corrosion cell effect to form micro Cu-Al galvanic local cells, which can serve as the favorable sites for branch tunnel initiation along the main tunnels to enhance specific capacitance of anode Al foil.

The purpose of the paper is to present an update and the latest results from work on a project which could be useful for maskless printed circuit board (PCB) manufacturing.

Copper is plated and etched using a novel electrochemical technique, electrochemical patterning by flow and chemistry, using a masked tool and fully exposed substrate. The micro patterns on the tool are replicated on the substrate via optimum design of the apparatus, choice of electrolyte chemistry and fluid flow.

Linear and square shapes ranging from 5 to 200 μm are transferred using the technique by electrochemical plating and etching. Up to 25 substrates could be processed using a single tool, which indicates that photolithography requirements can be greatly minimised.

The copper lines are transferred to relatively small substrates. The process needs to be scaled up to accommodate larger substrates in order to fully exploit its potential for PCBs.

The paper presents a fundamentally different approach to transfer micron scale pattern using a maskless technology. The platform technology involves using a mask to pattern each substrate; this work shows that micron scale patterns can be transferred without masking by optimising electrochemical reactor technology.

Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best.

Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp.

Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality.

Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.

Porous silicon (PS) was successfully fabricated using an alternating current photo-assisted electrochemical etching (ACPEC) technique. This study aims to compare the effect of different crystal orientation of Si n(100) and n(111) on the structural and optical characteristics of the PS.

PS was fabricated using ACPEC etching with a current density of J = 10 mA/cm² and etching time of 30 min. The PS samples denoted by PS₁₀₀ and PS₁₁₁ were etched using HF-based solution under the illumination of an incandescent white light.

FESEM images showed that the porous structure of PS₁₀₀ was a uniform circular shape with higher density and porosity than PS₁₁₁. In addition, the AFM indicated that the surface roughness of porous n(100) was less than porous n(111). Raman spectra of the PS samples showed a stronger peak with FWHM of 4.211 cm⁻¹ and redshift of 1.093 cm⁻¹. High resolution X-ray diffraction revealed cubic Si phases in the PS samples with tensile strain for porous n(100) and compressive strain for porous n(111). Photoluminescence observation of porous n(100) and porous n(111) displayed significant visible emissions at 651.97 nm (Eg = 190eV) and 640.89 nm (Eg = 1.93 eV) which was because of the nano-structure size of silicon through the quantum confinement effect. The size of Si nanostructures was approximately 8 nm from a quantized state effective mass theory.

The work presented crystal orientation dependence of Si n(100) and n(111) for the formation of uniform and denser PS using new ACPEC technique for potential visible optoelectronic application. The ACPEC technique has effectively formed good structural and optical characteristics of PS.

Component removal for rework and repair is traditionally achieved by re‐melting of the solder, but the exposure of the assembly or its component parts to repeated soldering/ desoldering cycles may cause both immediate damage and create a significant long term reliability hazard. Rework is labour intensive and requires skilled operators. Area array components further increase the complexity of the rework process because of the number and inaccessibility of the solder joints. There is a growing requirement to recycle/reclaim electronic waste, creating the need for an effective process for dismantling of printed circuit board assemblies (PCBAs). This paper will present a brief review of alternative non‐thermal techniques for rework or dismantling of conventional soldered assemblies, including both chemical etchants and mechanical techniques. Results will then be presented on trials of chemical etchants, where rates of solder removal consistent with realistic times for component removal have been readily achieved using commercially available tin‐lead strippers. Electrochemical techniques are also shown to be usable in specific applications, i.e. where electrical contact can be readily made to the solder joints to be removed, and have the advantage of reclaiming the removed solder directly from the electrolyte.

The purpose of this paper is to describe how fabricate solar cell based‐on porous silicon (PS) prepared by electrochemical etching process is fabricated and the effect of porosity layer on the solar cell performance is investigated.

The techniques used include SiO₂ thermal oxidation, ZnO/TiO₂ sputtering deposition and PS prepared by electrochemical etching. Surface morphology and structural properties of porous Si were characterized by using scanning electron microscopy. Photoluminescence and Raman spectroscopy measurements were also performed at room temperature. Current‐voltage measurements of the fabricated solar cell were taken under 80 mW/cm² illumination conditions. Optical reflectance was obtained by using optical reflectometer (Filmetrics‐F20).

Pore diameter and microstructure are dependent on anodization condition such as HF: ethanol concentration, duration time, temperature, and current density. On other hand, a much more homogeneous and uniform distribution of pores is obtained when compared with other wafer prepared with different electrolyte composition.

PS is found to be an excellent anti‐reflection coating against incident light when it is compared with another anti‐reflection coating and exhibits good light‐trapping of a wide wavelength spectrum which produce high efficiency solar cells (11.23 per cent).

In the production and overhaul of aero engines chemical and electrolytic surface treatment processes such as electrolytic degreasing, chemical and electrochemical etching, chemical descaling and chemical stripping of thermally sprayed coatings are used. In the course of some of these processes the heat resistant nickel and cobalt base alloys found in the “hot end” of the newer gas turbines are attacked. These superalloys have a common characteristic, namely, they are precipitation hardened. The alloying elements added for this purpose give rise to intermetallic compounds (carbides, nitrides, carbonitrides) which appear as inclusions of various shapes and sizes within the grain or at the grain boundaries. The conclusion from this work is that these intermetallics present as separate phases can be dissolved out by oxidative attack leaving pits. The separate processes and their objectives are detailed. It is shown in which process stages and in which solutions attack occurs. The inclusions have been analysed and the nature of the attack is illustrated. We conclude from this work, which has embraced seven nickel and cobalt base materials, that certain processes or process steps cannot be permitted on these alloys. For cleaning and etching alternative processes are given. For descaling a new compatible process was evaluated and will be discussed in a second report.

The purpose of this paper is to study an electrolytic etching method to prepare fine lines on printed circuit board (PCB). And the influence of organics on the side corrosion protection of PCB fine lines during electrolytic etching is studied in detail.

In this paper, the etching factor of PCB fine lines produced by new method and the traditional method was analyzed by the metallographic microscope. In addition, field emission scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to study the inhibition of undercut of the four organometallic corrosion inhibitors with 2,5-dimercapto-1,3,4-thiadiazole, benzotriazole, l-phenylalanine and l-tryptophan in the electrolytic etching process.

The SEM results show that corrosion inhibitors can greatly inhibit undercut of PCB fine lines during electrolytic etching process. XPS results indicate that N and S atoms on corrosion inhibitors can form covalent bonds with copper during electrolytic etching process, which can be adsorbed on sidewall of PCB fine lines to form a dense protective film, thereby inhibiting undercut of PCB fine lines. Quantum chemical calculations show that four corrosion inhibitor molecules tend to be parallel to copper surface and adsorb on copper surface in an optimal form. COMSOL Multiphysics simulation revealed that there is a significant difference in the amount of corrosion inhibitor adsorbed on sidewall of the fine line and the etching area.

As a clean production technology, electrolytic etching method has a good development indicator for the production of high-quality fine lines in PCB industry in the future. And it is of great significance in saving resources and reducing environmental pollution.

Nanogap electrodes have important applications in power saving devices, electrochemical sensors and dielectric detections of biomolecules. The purpose of this paper is to report on the fabrication and characterization of polysilicon nanogap patterning using novelties technique.

Polysilicon material is used to fabricate the nanogap structure and gold is used for the electrode and two chrome masks are used to complete this work; the first mask for the nanogap pattern and a second mask for the electrode. The method is based on the control of the coefficients (temperature and time) with an improved pattern size resolution thermal oxidation.

Physical characterization by scanning electron microscopy (SEM) demonstrates such nanogap electrodes could be produced with high reproducibility and precision. Electrical characterization shows that nanogap enhanced the sensitivity of the device by increase the capacitance and the conductivity as well. They have also good efficiency of power consumption with high insulation properties.

With this technique, there are no principal limitations to fabricating nanostructures with different layouts down to several different nanometer dimensions. The paper documents the fabrication of nanogaps electrodes on a polysilicon, using low‐cost techniques such as vacuum deposition and conventional lithography. Polysilicon is a low‐cost materials and has desirable properties for semiconductor applications. A method of preparing a nanogap electrode according to the present innovation has an advantage of providing active surface that can easily be modified for immobilizations of biomolecules.