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Lowering of investment barriers between European nations has led to increasing integration of their capital markets. Consequently, global investors may be well‐advised to evaluate European stocks, not on the basis of the country of listing, but on the basis of the transnational industrial sector to which the stocks belong. This study utilizes performance measures, grounded in modern portfolio theory, to assess the risk‐adjusted return that has accrued to major transnational industrial sectors in Europe, such as consumer products, technology, utilities and financial services. The empirical documentation generated here can be used by international investors as input in decision making for sectorial allocation of funds in the European component of their global stock portfolios.

Although Multi-Layer Ceramic Capacitors (MLCC) are known for its better frequency performance and voltage handling capacity, but under various environmental conditions, its reliability becomes a challenging issue. In modern era of integration, the failure of one component can degrade or shutdown the whole electronic device. The lifetime estimation of MLCC can enhance the reuse capability and furthermore, reduces the e-waste, which is a global issue.

The residual lifetime of MLCC is estimated using empirical method i.e. Military handbook MILHDBK2017F, statistical method i.e. regression analysis using Minitab18.1 as well as intelligent technique i.e. artificial neural networks (ANN) using MATLAB2017b. ANN Feed-Forward Back-Propagation learning with sigmoid transfer function [3–10–1–1] is considered using 73% of available data for training and 27% for testing and validation. The design of experiments is framed using Taguchi’s approach L16 orthogonal array.

After exploring the lifetime of MLCC, using empirical, statistical and intelligent techniques, an error analysis is conducted, which shows that regression analysis has 97.05% accuracy and ANN has 94.07% accuracy.

An intelligent method is presented for condition monitoring and health prognostics of MLCC, which warns the user about its residual lifetime so that faulty component can be replaced in time.

Managing supply risk is gaining in importance in the tightly interconnected global economy. Identifying the relevant risks is the foundation of any risk management process. Therefore, the purpose of this paper first is to provide a short introduction to supply risk management, before focussing on the identification of such risks in more detail. A holistic framework of the identified supply risks, which distinguishes between risk dimensions and risk factors in manufacturing upstream supply networks, is proposed.

This study applies a mixed methods research approach. Data are collected based on a structured literature review in combination with the analysis of company-specific documents and semi-structured expert interviews. Subsequently, a deductive content analysis is carried out to derive a holistic framework of supply risks, adapted to the manufacturing industry. For the external validation of the conceptual supply risk framework, additional experts from several manufacturing companies were consulted.

Based on the definition and delimitation of supply risk, a categorization of supply risks is developed. The relevant literature, as well as expert interviews, lead to the distinction of six supply risk dimensions: quality, delivery, collaboration, economic, ambience and compliance. A total of 27 risk factors can be assigned to these dimensions. A holistic foundation for the management of supply risk is thus created.

This study provides a holistic framework of relevant supply risks in the context of the manufacturing industry. This overview of identified risks offers a novel perspective on risk in manufacturing supply networks that can be helpful in researching assessment and mitigation strategies. Despite the high relevance and popularity of this field of research, such an overview with a focus on manufacturing had not yet been made available in the literature. Building thereon, management approaches can now be developed to handle the risk arising from the upstream of the supply network.

Capacitors are one of the most common passive components on a circuit board. From a tiny toy to substantial satellite, a capacitor plays an important role. Untimely failure of a capacitor can destruct the entire system. This research paper targets the reliability assessment of tantalum capacitor, to reduce e-waste and enhance its reusable capability.

The residual lifetime of a tantalum capacitor is estimated using the empirical method, i.e. military handbook MILHDBK2017F, and validated using an experimental approach, i.e. accelerated life testing (ALT). The various influencing acceleration factors are explored, and experiments are designed using Taguchi's approach. Empirical methods such as the military handbook is used for assessing the reliability of a tantalum capacitor, for ground and mobile applications.

After exploring the lifetime of a tantalum capacitor using empirical and experimental techniques, an error analysis is conducted, which shows the validity of empirical technique, with an accuracy of 95.21%.

The condition monitoring and health prognostics of tantalum capacitors, for ground and mobile applications, are explored using empirical and experimental techniques, which warns the user about its residual lifetime so that the faulty component can be replaced in time.

The advent of novel advanced packaging technologies such as multilayer thin‐film interconnect, combined with continuous improvements in IC clock speed and circuit performance, has placed extreme demands on electronics packaging and package materials. Aluminium nitride (AIN) ceramic offers significant opportunities and advantages for package design, particularly where the effective thermal management and overall reliability of large devices are a high priority. AIN has already been successfully employed at the substrate level for the enhanced thermal relief of power devices. Examples of these applications include heat sinks and device mounts for thyristor modules, power transistors, solid state relays, power SCRs, switching modules, LEDs and various RF package configurations. Both bare and metallised AIN substrates are beginning to find application as a substitute for beryllia (BeO) in mass market and high reliability automotive electronics applications. Successfully implementing AIN in a high level electronics packaging application requires a systems approach in which the intrinsic properties of AIN are considered as ‘first principles’ in shaping the package design process. The unique physicochemical and mechanical properties of AIN require the development of specialised metallisation and co‐firing processes to fabricate the advanced components necessary for hermetic packaging of complex devices and multichip modules. This paper presents a practical and mass manufacturable AIN‐based package tailored to these high level applications. The package design is unique in that it provides for the total separation of the electrical‐signal conduction from the mechanical support/mounting functions of the package. Such a separation of the functions improves both the package durability and reliability relative to currently available electronics packages of conventional designs.

The paper describes a new electro‐optical board technology, based on the discrete wiring principle. Isolated copper wires are embedded in the circuit board to realise the electrical interconnections. Glass optical fibres are embedded to obtain optical interconnections. The technology allows for crossovers and for electrical and optical interconnections on one layer of interconnection. As the technology can be applied on the level of package or multichip module, circuit board and backpanel, it has the ability to offer a complete solution for chip to chip electrical and optical interconnections. The paper will describe the basic manufacturing technology of the boards. The benefits of the technology from a system designer's viewpoint will be addressed. The problem of coupling light in and out of the embedded optical fibres will be discussed and the realisation of a first on‐board optical link via embedded optical fibres will be described.

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.

In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.

The choice of high pin count ASIC packages has a major impact on the total cost and performance of the whole packaging system. Six different types of ASIC packages have been compared with respect to production aspects, availability, reliability, thermal and electrical properties and cost. Recommendations for the proper choice of packages for different types of applications are given. All packages have been directly assembled to PWBs in order to study problems with handling, solder process, testing and repairability. Some of the assembled packages have been temperature cycled in order to test the solder joint reliability. The pin grid array packages are the most frequently used high pin count packages today. However, they are expensive and through‐hole mounting reduces the routing capability of the board. Pad area array packages are a hermetic alternative with a lower price for the package as well as very good thermal and electrical properties, but they need to be mounted on expensive PWBs. Another surface mountable package which is hermetic is the ceramic leaded chip carrier with fine lead pitch. This package is even more expensive than the pin grid array package and is difficult to handle. In the future, non‐hermetic alternatives will probably predominate. Plastic quad flat pack and TapePak can be used below 160–180 leads, while direct assembled TAB would be the best alternative for very high pin counts. Before one can use non‐hermetic packages in telecom products, a large qualification programme must be performed to evaluate the long‐term reliability.