Search results

In this study a multilayer hybrid circuit for high frequency digital systems using Cu conductors was fabricated. The available Cu pastes were evaluated in terms of their applicability and a complex multilayer interconnection circuit was realised and optimised using both the DuPont and Heraeus Cu thick film systems. Also, AI‐1% Si wedge bonding on Cu thick film was investigated. The pull strengths were measured before and after ageing (high temperature storage). Results indicate that Al wire bonding on Cu is technologically feasible and gives no reliability problems.

This paper outlines methods and results of wetting, leaching and adhesion analyses on copper thick film conductors over alumina and multilayer glasses after different processing conditions. The intention is to provide a better background for evaluating and optimising materials and processing conditions in copper thick films and working out quick, reliable and quantitative methods for better characterisation of copper conductors in production. For these reasons the following methods were used: (a) wetting and leaching analyses with a scanning wetting balance, working in nitrogen, (b) pull tests with solder contacts on copper thick film conductors after soldering, ageing and thermal cycling, and (c) some additional surface analyses (REM, EDX, Auger) for a better understanding of copper pastes and their material interactions, when processed under different conditions. The results are summarised under three general aspects: surface structure and wetting of copper thick films, wetting and leaching of various copper thick films after different processing conditions, and finally the influence of different wetting properties of such surfaces on the solder adhesion strength after soldering, ageing and thermal cycling. The results give good insight into the various interactions of copper thick films with their substrate materials and confirm the ability of the described wetting and leaching analyses for these purposes.

In this paper, it is shown that the so‐called in‐situ electrical measurement technique is a valuable tool for understanding failure mechanisms in thick film dielectrics. The technique makes it possible to measure important electrical characteristics of thick film dielectric systems in the temperature range from room temperature up to 900°C. This information is essential to understand failure mechanisms and to optimise the system with respect to quality and reliability. Mainly two electrical properties have been investigated: (i) the electrical resistance of the dielectric as a function of temperature and (ii) the spontaneous electromotive force occurring at higher temperatures between two metal layers with the dielectric in between. A significant result of the work is the observation of a close correlation between the leakage current measured through the dielectric at elevated temperatures, and the ability of the dielectric to resist shorting and blistering effects during the preparation of circuits. Secondly, from in‐situ voltage measurements, it was confirmed that the mixed metallurgy system Au(bottom)‐dielectric‐Ag(top) acts at 850°C as a spontaneous battery, and the battery voltage (i.e., the spontaneous electromotive force) was measured. Depending on the type of dielectric, a battery voltage up to 200 mV between the two metal layers was observed. As a result of this spontaneous electromotive force, blistering occurs. The battery voltage was shown to be much smaller in unmixed metallurgy systems with Ag(bottom)‐dielectric‐Ag(top) or Au(bottom)‐dielectric‐Au(top). However, if an external voltage of 300 mV is applied to such a system during a temperature profile up to 850°C, blisters can also be induced. This shows unambiguously that blistering is a voltage driven effect.

Presents the thermo‐mechanical modelling of a new type of area array package: the flip chip on polymer stud grid array (PSGA). The objective is to optimise the material and geometrical design of this PSGA package and the flip chip assembly in order to achieve the highest thermal fatigue reliability for the solder joints in this structure. A parameterised non‐linear finite element model is used to calculate the inelastic strains induced in the solder joints due to thermal cycling. The techniques of design of experiments (DOE) and response surface modelling (RSM) enhance the parameter sensitivity analysis and optimisation of the PSGA design. After the optimisation of the structure, a very high solder joint fatigue reliability of this flip chip to PSGA package has been achieved.

A novel interconnect technology, introducing thin film on a laminate substrate base, is presented. A specially constructed laminate board is used as a substrate for the thin film build‐up process. The main characteristics of the laminate core substrate are the z‐axis electrical connections, the absence of holes in the substrate and the very flat nature of the top surface. As a result, the base substrate can be processed further in a thin film processing line. The manufacturing and properties of these substrates are discussed.

The thin film multilayer multichip module technology (MCM‐D) was originally used for the interconnection of high speed digital circuits in a single module. Nowadays, the technology is more and more evolving towards use in the interconnection of RF and microwave circuits with integrated passive components. This paper gives an overview of this evolution towards microwave MCM‐D technology and the recent advances with respect to the integration of high quality passive components. With a discussion on the flip chip mounting of active devices, the link towards fully integrated high frequency front‐end systems is pointed out.

High Q on‐chip inductors and low loss on‐chip interconnects and transmission lines are an important roadblock for the further development of Si‐based technologies at RF and microwave frequencies. In this paper, inductors are realized on standard Si wafers (20 Ω.cm) using MCM‐D processing. This consists of realizing two low K dielectric layers (BCB) and a thick Cu interconnect layer. Inductors with 5 μm lines and spaces are demonstrated for a 5 μm thick Cu layer, hereby leading to a very compact and high performance inductors: Q‐factors in the range of 25 to 30 have been obtained for inductances in the range of 1 to 5 nH. It is also shown how the Q‐factor and resonance frequency vary as a function of the inductor layout parameters and the thickness of the BCB and Cu layers. The realized 50 Ω CPW lines (lateral dimension of 40 μm) have a measured loss of only 0.2 dB/mm at 25 GHz.