Search results

The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications.

To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO₂/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used.

In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined.

The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

Describes the key attributes of MEMS technology and existing and future business opportunities. Discusses the various stages in the fabrication of MEMS devices and offers guidance regarding the selection of processing methods for deposition, lithography and etching. Also describes the MEMS‐Exchange program and associated network of fabrication centres.

The purpose of this paper is to present a selective wet‐etching method of boron doped low‐pressure chemical vapour deposition (LPCVD) polysilicon film for the realization of piezoresistors over the bulk micromachined diaphragm of (100) silicon with improved yield and uniformity.

The method introduces discretization of the LPCVD polysilicon film using prior etching for the grid thus dividing each chip on the entire wafer. The selective etching of polysilicon for realizing of piezoresistors is limited to each chip area with individual boundaries.

The method provides a uniform etching on the entire silicon wafer irrespective of its size and leads to economize the fabrication process in a batch production environment with improved yield.

The method introduces one extra process step of photolithography and subsequent etching for discretizing the polysilicon film.

The method is useful to enhance yield while defining metal lines for contact purposes on fabricated electronic structures using microelectronics. Stress developed in LPCVD polysilicon can be removed using proposed approach of discretization of polysilicon film.

The work is an outcome of regular fabrication work using conventional approaches in an R&D environment. The proposed method replaces the costly reactive ion etching techniques with stable reproducibility and ease in its implementation.

Driven by the demand for higher density in electronic packaging, each signal plane of printed wiring board must accommodate more conductors. As a result, conductor width is becoming narrower each year. This chapter reviews some of the important steps of forming finer line conductors in printed wiring boards, such as surface preparation, plating/etching, photo‐exposure, automatic optical inspection, etc.

When designing the electrode widths of the electrode-width-weighted (EWW) input interdigital transducers (IDTs) according to the envelope amplitudes of the wavelet function, the EWW wavelet transform processor (WTP) using surface acoustic wave (SAW) devices can be fabricated. The electrode widths have influence on the frequency characteristic of the EWW WTP using SAW devices. The purpose of this research is to solve the influence of the electrode width accuracy on the frequency characteristic of the EWW WTP using SAW devices.

In order to solve the influence of the electrode width accuracy on the frequency characteristics of the EWW WTP using SAW devices, the function between the electrode widths and the −3 dB bandwidth is derived. That the −3 dB bandwidth varies as the electrode widths is known according to this function so that the exposure time and the etching are presented as the two key problems.

Solutions to these problems are achieved in this study. As long as there is accurate exposure time, the precision IDTs (i.e. the precision electrode widths) will be obtained. The accuracy of the exposure time for the EWW WTP using SAW devices is ±1 per cent. Because the dry etching is a type of etching technology in gas medium, it can etch nanometer lines, even more fine lines, so that the dry etching is used in EWW WTP using SAW devices.

Research highlights solving the influence of the electrode width accuracy on the frequency characteristic for the EWW WTP using SAW devices; deriving the function between the electrode widths and the −3 dB bandwidth (it is known from this function that the −3 dB bandwidth varies as the electrode widths); and presenting the exposure time and the etching as two key problems.

There are many advantages of microvia: it requires a much smaller pad, which saves the board size and weight; with microvia, more chips can be placed in less space or a smaller PCB, which results in a low cost; and with microvia, electrical performance improves due to a shorter pathway. Basically, there are five major processes for microvia formation: NC drilling; laser via fabrication including CO₂ laser, YAG laser, and excimer; photo‐defined vias, wet or dry; etch via fabrications including chemical (wet) etching and plasma (dry) etching; and conductive ink formed vias, wet or dry. This paper will discuss the materials and processes of these five major microvia formation methods. At the end, eight key manufacturers from Japan will be briefly illustrated for their research status and current capability of producing smallest microvia.

Porous silicon (Si) was fabricated by using three different wet etching methods, namely, direct current photo-assisted electrochemical (DCPEC), alternating CPEC (ACPEC) and two-step ACPEC etching. This study aims to investigate the structural properties of porous structures formed by using these etching methods and to identify which etching method works best.

Si n(100) was used to fabricate porous Si using three different etching methods (DCPEC, ACPEC and two-step ACPEC). All the samples were etched with the same current density and etching duration. The samples were etched by using hydrofluoric acid-based electrolytes under the illumination of an incandescent lamp.

Field emission scanning electron microscopy (FESEM) images showed that porous Si etched using the two-step ACPEC method has a higher porosity and density than porous Si etched using DCPEC and ACPEC. The atomic force microscopy results supported the FESEM results showing that porous Si etched using the two-step ACPEC method has the highest surface roughness relative to the samples produced using the other two methods. High resolution X-ray diffraction revealed that porous Si produced through two-step ACPEC has the highest peak intensity out of the three porous Si samples suggesting an improvement in pore uniformity with a better crystalline quality.

Two-step ACPEC method is a fairly new etching method and many of its fundamental properties are yet to be established. This work presents a comparison of the effect of these three different etching methods on the structural properties of Si. The results obtained indicated that the two-step ACPEC method produced an etched sample with a higher porosity, pore density, surface roughness, improvement in uniformity of pores and better crystalline quality than the other etching methods.

This extract from a recent survey of micro‐machining in the USA outlines the techniques and difficulties of this ‘upwardly mobile’ technology.

Porous silicon (PS) was successfully fabricated using an alternating current photo-assisted electrochemical etching (ACPEC) technique. This study aims to compare the effect of different crystal orientation of Si n(100) and n(111) on the structural and optical characteristics of the PS.

PS was fabricated using ACPEC etching with a current density of J = 10 mA/cm² and etching time of 30 min. The PS samples denoted by PS₁₀₀ and PS₁₁₁ were etched using HF-based solution under the illumination of an incandescent white light.

FESEM images showed that the porous structure of PS₁₀₀ was a uniform circular shape with higher density and porosity than PS₁₁₁. In addition, the AFM indicated that the surface roughness of porous n(100) was less than porous n(111). Raman spectra of the PS samples showed a stronger peak with FWHM of 4.211 cm⁻¹ and redshift of 1.093 cm⁻¹. High resolution X-ray diffraction revealed cubic Si phases in the PS samples with tensile strain for porous n(100) and compressive strain for porous n(111). Photoluminescence observation of porous n(100) and porous n(111) displayed significant visible emissions at 651.97 nm (Eg = 190eV) and 640.89 nm (Eg = 1.93 eV) which was because of the nano-structure size of silicon through the quantum confinement effect. The size of Si nanostructures was approximately 8 nm from a quantized state effective mass theory.

The work presented crystal orientation dependence of Si n(100) and n(111) for the formation of uniform and denser PS using new ACPEC technique for potential visible optoelectronic application. The ACPEC technique has effectively formed good structural and optical characteristics of PS.

While the interest in alternative metalization processes for the manufacturing of printed wiring boards is extremely keen, the long‐term reliability of plated through holes fabricated with these electroless copper alternatives remains in question. However, during the last three years, significant process improvements have been made in the direct metalization process based on a patented dispersion of graphite. This paper will describe the technology in detail and present data on the reliability and versatility of the graphite based direct metalization process.