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This research paper aims to investigate the change detection filter technique with a decision tree-based event (fault type) classifier for recognizing and categorizing power system disturbances on the high-voltage DC (HVDC) transmission link.

A change detection filter is used to the average and differential current components, which detects the point of fault initiation and records a change detection point (CDP). The half-cycle differential and average currents on both sides of the CDP are sent through the signal processing unit, which produces the respective target. The extracted target indices are sent through a decision tree-based fault classifier mechanism for fault classification.

In comparison with conventional differential current protection systems, the developed framework is faster in fault detection and classification and provides great accuracy. The new technology allows for prompt identification of the fault category, allowing electrical grids to be restored as quickly as possible to minimize economic losses. This novel technology enhances efficiency in terms of reducing computing complexity.

Setting a threshold value for identification is one of the limitations. To bring the designed system into stability condition before creating faults on it is another limitation. Reducing the computational burden is one of the limitations.

Creating a practical system in laboratory is difficult as it is a HVDC transmission line. Apart from that, installing rectifier and converter section for HVDC transmission line is difficult in a laboratory setting.

The suggested scheme’s importance and accuracy have been rigorously validated for the standard HVDC transmission system, subjected to various types of DC fault, and the results show the proposed algorithm would be a feasible alternative to real-time applications.

This paper aims to focus on the implementation of the International Electrotechnical Commission (IEC) 61850–9-2 standard based process bus with merging units (MUs) and sampled values (SV) to improve the protection and control systems. The digital process interface is important to be included on the process bus level.

The IEC 61850–9-2 process bus standard is not extensively used in regard to SV when the IEC 61850 standard is implemented by power utilities. Many protection and control intelligent electronic devices (IEDs) are connected to a substation communication network, routers and switches using fibre-optic linked Ethernet. However, inductive current transformers (CTs) and voltage transformers (VTs) secondary circuits are still hardwired to the IEDs. The paper highlight issues with the copper wires for currents signals and how these issues can be eliminated by using the MUs and the SV protocol. The voltage regulator control IED of each transformer is required to regulate the voltage level of the secondary side bus bar it is connected to. All the regulating IEDs of parallel-connected transformers are required to communicate with each other to share information. They collectively control the bus bar voltage depending on the switching configuration of the parallel transformers.

It is shown that process bus information such as the high voltage switchgear status information of primary plant in the yard, can be used to improve the substation protection and control systems. The power transformer protection and voltage regulator control are focused on.

The deliverables of the research work can be applied in: The Centre for Substation Automation and Energy Management systems of the Department of Electrical Engineering, power utilities and other establishments using power systems and digital substations in the electrical supply industry. The research work on the thesis led to the development of a laboratory test-bench where students can learn and understand the basics of the IEC 61850–9-2 SVs principles. The test-bench components such as the IEDs, real-time digital simulator, standalone MUs and Ethernet equipment can be used for future research applications. The test-bench can be used to demonstrate during course work for students at the University, the basics of digital substations using a process bus network with IEDs, MUs and Ethernet equipment.

The research work showed where lab equipment is getting outdated and future equipment will be required for research work in IEC 61850–9-2 process bus.

Power utilities can benefit from implementing the IEC 61850 part 9–2 of the standard and by using MUs and other process interface information in substations. A cost reduction in high voltage equipment, substation installation and commissioning costs and better performance of protection and control system can be achieved.

This work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.

Integrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.

Measured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.

This paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.

Interturn winding faults, one of the most important causes of power transformers failures, cannot be detected by existing detection methods until they develop into high‐level faults with more severe damage to the transformer. The purpose of this paper is to describe development of a new discrete wavelet transform (DWT) based approach for detection of winding interturn faults.

The following approach was accomplished for development of the proposed fault detection method in this study. The DWT was first applied to decompose the terminal current signals of a transformer, which in turn were obtained from simulations using a finite elements method model of the transformer, into a series of wavelet components. Based on the characteristic features associated with interturn faults extracted from the decomposed waveforms of the terminal currents, a detection scheme was developed. An experimental setup was used to validate the proposed detection method.

The results of this study demonstrate the efficacy of DWT applied on terminal currents of the transformer to identify interturn faults on the windings well before such faults lead to a catastrophic failure. It is believed that, based on the present findings, there definitely exists scope for improving interturn fault diagnosis with wavelet transform.

Performing more detailed studies to find all relevant characteristics of the wavelet transform in this application, identifying the location of the faulted turns along winding, applying the method for indicating early stages of turn insulation deterioration and evaluating other type of wavelets for this application would be some future directions of this research.

With the proposed method, it is becoming possible to detect early signs of the fault occurrence, so that the necessary corrective actions can be taken to prevent long‐lasting outages and reduce down times of the faulty power transformer. The method will be particularly useful as a complement for the classical protection devices of the power transformers.

Some recent studies have been carried out regarding the application of DWT for discrimination between an internal fault and other disturbances such as magnetizing inrush and external faults. This paper extends those studies for the detection of interturn faults using more quantitative and qualitative characteristics features.

The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.

The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.

Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.

This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

To describe and extend existing concepts of discrete electromagnetism in a unified formalism; to give examples for the usefulness of the presented ideas for our theoretical work, especially with regard to energy.

After a concise introduction to the mathematical concepts of discrete electromagnetism, we introduce continuous de Rham currents and give their discrete counterpart. We define operators acting upon discrete currents, and apply the theory to electromagnetism.

de Rham current theory yields a mathematical framework for the discussion of discrete electromagnetic problems: The focus is on energy‐balance equations; a discrete Lagrangian can be defined for various modeling problems; the Galerkin approach fits nicely into the proposed formalism; boundary terms in discrete formulations are an implicit feature to the theory.

In this paper, we use the interpolation of discrete fields by Whitney forms on a simplicial cell complex. The resulting discrete formulation is identical to a Galerkin finite‐element method. Other numerical techniques that do not resort to Whitney‐form interpolation can equally be discussed in de Rham‐current terminology.

Rather than a novel numerical technique, the paper presents a unified mathematical framework for the discussion of different practical approaches. We advocate a canonical treatment of energy‐related quantities and of boundary terms in discrete formulations.

This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

The aim of the research was to find a structure of the power electronics controlled current source with extended pass band, which would better match a source output current within an input (reference) signal. Also, pulse modulation components in output current of current source should be minimized.

The power electronics controlled current source utilizes both, the concept of the inductor with variable (controlled) inductance located at the output of an inverter and the concept of the multi‐channel (interleaved) inverter. The small signal (linear) and simulation models of an active filter have been investigated.

The work presents the concept of 1‐phase active shunt filter with utilization of the power electronics current source about extended pass‐band.

The research should be continued to achieve stability of the electrical system with variable parameters of the power network and receiver.

The research will be continued towards realization of a laboratory model of a 3‐phase active shunt filter with the DSP based control module.

Social implications are difficult to determine.

The paper presents a new concept of the precision power electronics controlled current source with the extended pass‐band. The controlled current source is the fundamental block of a power electronics active shunt filter.

This paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM).

The proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V.

The proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings.

The proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.

Changes in external auditing over four decades motivates a historical investigation of how client employees' perceptions of auditors have changed across this period.

This paper uses a longitudinal quasi-experiment to compare current client employees' perceptions of the auditor with results from 1972.

Changes in client employees' perceptions of the audit, its usefulness and of auditor-client conflict suggest increases in auditor independence. However, this paper also finds that despite decades of efforts to strengthen auditor independence and skepticism, the primary analogy client employees apply to the external auditor remains “consultant”.

The findings contribute to the discussion of whether regulatory and standard changes in the audit environment have changed aspects of client employees' perceptions of auditors.

The paper contributes by presenting a unique approach to partially replicating a historic study using a quasi-experimental research design.