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This article has been withdrawn as it was published elsewhere and accidentally duplicated. The original article can be seen here: 10.1108/01445159710163481. When citing the article, please cite: David C. Whalley, Samjid H. Mannan, David J. Williams, (1997), “Anisotropic conducting adhesives for electronic assembly”, Assembly Automation, Vol. 17 Iss 1 pp. 66 - 74.

Presents some experimental and theoretical results from research exploring the design rules and relevant process parameters in the assembly of electronic components using anisotropic conductive adhesive materials. The experimental configurations studies have geometries representative of flip‐chip and micro ball grid array chip scale packaging. Evaluates a range of materials combinations, including (random filled) adhesive materials based on both thermoplastic and thermo‐setting resin systems, combined with both glass reinforced polymer printed circuit board and silver palladium thick film on ceramic substrate materials. Also presents a summary of assembly experiments which have been conducted using a specially developed instrumented assembly system. This test rig allows the measurement of the process temperatures and pressures and their relationship with the consequent bondline thickness reduction and conductivity development. Finally summarizes the capabilities of models which have been developed of the assembly process and of the final joint properties.

The purpose of this paper is to present an outline of the development of a new process for the formation of flip‐chip interconnections using metal coated polymer microparticles.

Metal coated polymer microparticles were selectively deposited onto the bondpads of integrated circuits using electrophoresis. Thermocompression bonding was then used to bond the devices to substrates.

Particles obtained a positive surface charge following immersion in an acidic solution and this surface charge allowed the particles to be deposited electrophoretically directly onto the bondpads of an integrated circuit without the need for patterning. Thermocompression bonding of nickel/gold coated particles to gold coated substrates was achieved at temperatures as low as 160°C.

Further work is needed to test this approach using integrated circuits with finer pitch, and to use patterned substrates for assembly and reliability measurements.

This paper presents a new method for the deposition of metal coated polymer microparticles without the need for any masking or patterning processes for the formation of interconnections on integrated circuits.

Previous models of temperature development during the reflow soldering process have typically used commercially available, general purpose, finite difference/finite element modelling tools to create detailed three dimensional representations of both the product and of the reflow furnace. Such models have been shown to achieve a high degree of accuracy in predicting the temperatures a particular PCB design will achieve during the reflow process, but are complex to generate and analysis times are long, even when using modern high performance computer workstations.This paper will report on the development of a simplified model of the process, which uses less complex representations of both the product and the process, together with a simple numerical solver developed specifically for this application, whilst achieving an accuracy comparable with more detailed models. In the simplified model, the product is divided into elements, which are represented using a two‐dimensional mesh of thermal conductances linking thermal masses. The values of these conductances and masses are calculated based on the averaged properties of the PCB material and attached components within the area of each of the elements. The representation of the specific reflow furnace is based on measurements of the temperature and level of thermal convection at each point along the length of the furnace, thereby avoiding the necessity of making detailed measurements of the furnace geometry and air flow velocities. The combination of these two simplification techniques allow the reduction of analysis time for a relatively simple PCB from in the order of an hour on a high performance Unix workstation to under a second on a Pentium class PC running Microsoft Windows.

The encapsulation of electronic assemblies within thermoplastic polymers is an attractive technology for the protection of circuitry used in harsh environments, such as those experienced in automotive applications. However, the relatively low‐thermal conductivity of the encapsulating polymer will introduce a thermally insulating barrier, which will impact on the dissipation of heat from the components and may result in the build‐up of stresses in the structure. This paper therefore seeks to present the results from computational models used to investigate the thermal and thermo‐mechanical issues arising during the operation of such electronic modules. In particular, a two‐shot overmoulded structure comprising an inner layer of water soluble and an outer layer of conventional engineering thermoplastics was investigated, due to this type of structure's potential to enable the easy separation of the electronics from the polymer at the end‐of‐life for recycling.

Representative finite element models of the overmoulded electronic structures were constructed and the effects of the polymer overmould were analysed through thermal and thermo‐mechanical simulations. Investigations were also carried out to explore the effect of materials properties on the overmoulded structure.

Models have shown that some power de‐rating of components is required to prevent temperatures exceeding those in unencapsulated circuits and have quantified the benefits of adding thermally conductive fillers to the polymer. Simulations have also clearly demonstrated the benefits of foamed polymers in reducing thermal stresses in the assemblies, despite their poorer thermal conductivity compared with solid polymers.

The paper illustrates the thermal issues affecting the overmoulded electronics and gives some guidelines for improving their performance.

Non‐planarity of assemblies and co‐planarity variation effects on anisotropic conductive adhesive (ACA) assemblies have been a concern for ACA users since the materials are first devised. The primary objective of this paper is to introduce a new experimental method for studying co‐planarity variation effects on ACA assemblies.

The approach simulates non‐planarity through deliberate chip rotation during the ACA bonding process, thereby locking different levels of co‐planarity variation into ACA test assemblies. Scanning electron microscope (SEM) analysis and electrical joint resistance measurement using the four wire resistance (FWR) method are used to mechanically and electrically examine the connection quality of the ACA assemblies bonded with non‐planar joints, for which the chip and substrate patterns are specially designed to allow joint resistance measurement using the FWR method.

Typical experiments and their results are presented and analysed. The bond thickness differences between the SEM measurements and calculations indicate that the real rotations are smaller than those predicted by the calculations. The typical experimental results show that the joint resistance reduces as the deformation increases until reaching a relatively stable value after a certain deformation degree.

The average joint resistances in the rotated samples are all bigger than those measured in the un‐rotated samples. This raises the question as to whether the joint resistances of ACA assemblies are more significantly affected by other affects of non‐planarity than just by its effect on bond thickness. However, before this can be confirmed, more research must be done to check if this behaviour happens for different bonding forces.

This paper reports a novel and simple experiment that can be used to examine the effects of co‐planarity variation on the electrical performance of ACA assemblies, by creating different bond thicknesses that are normally difficult to achieve by changing the bonding pressure, since ACA bond thicknesses are not linearly related to the bonding force. The merit of the technique is that there is no need to manufacture chip bumps and substrate pads with different geometries, or to control the bond pressure, to achieve bond thickness variation in ACA assemblies.

As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150‐200μm. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127μm.