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Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control.

All the modules used to design a RAM cell are designed using multilayer approach in QCA framework.

The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation.

Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures.

The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues.

The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking).

In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-μm CMOS process. Simulation results show that good conformance between analytical equations and simulation results.

The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.

The purpose of the paper is to focus on the development of an asynchronous application which helps to compute the least common multiple (LCM) of two 4‐bit numbers.

The paper discusses a top‐down approach where the design starts from a high level of abstractions and is refined until the transistor level is reached. Circuit techniques rather than optimization have been emphasized in this paper.

Asynchronous circuits are the low power alternatives to the synchronous ones. Even through asynchronous circuits are less developed, they have tremendous potential of becoming the main‐stream design technology in future.

The reader is able to gain a wider perspective and detailed knowledge of the implementation of the handshaking circuits, the signaling protocols, the control path, and the data path among others.

Present and future development of laser processing as a production technique for modifying semiconductor devices, improving yields, and decreasing development times are described. Current applications covered include thick‐ and thin‐film resistor trimming, deposited film and polysilicon resistors on silicon trimming and redundant memory repair. Emerging applications include microcircuit mask making and capacitor trimming. Examples of processes still under development include selective annealing, minority‐carrier lifetime doping, and device diagnostics by laser imaging.

INDUSTRIAL consultants are being increasingly employed both here and in the United States. It is natural that much of their work should fall within the field of work study since the usual reason for calling them in is to secure greater productivity. Such incursions are sometimes looked at askance by those assigned to that particular role in a company. This understandable human attitude will not be exorcised by implying that consultants are a race of infallible beings whose job is to impose superior methods on the permanent staff.

Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay.

In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools.

The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits.

A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

Sensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor network hardware is their limited available energy resource, which makes the low power design of these sensors important. This paper aims to present a low power sensor which can detect sound waveform signatures.

A novel mixed signal hardware is presented to correlate the received sound signal with a specific sound signal template. The architecture uses pulse width modulation and a single bit digital delay line to propagate the input signal over time and analog current multiplier units to perform template matching with low power usage.

The proposed method is evaluated for a chainsaw signature detection application in forest environments, under different supply voltage values, input signal quantization levels and also different template sample points. It is observed that an appropriate combination of these parameters can optimize the power and accuracy of the presented method.

The proposed mixed signal architecture allows voltage and power reduction compared with conventional methods. A network of these sensors can be used to detect sound signatures in energy limited environments. Such applications can be found in the detection of chainsaw and gunshot sounds in forests to prevent illegal logging and hunting activities.

We wish our readers, especially in this war year, the Best of the Season's Good Things!

This study aims to provide a comprehensive review and bibliometric analysis of the literature in the field of science, technology, engineering and mathematics (STEM) education over the past 15 years, with a specific focus on global distribution and research trends.

This study collected 1,718 documents from the Web of Science (WOS) database and analyzed their timeline distribution, geographical distribution, research topics, subject areas, learning stages and citation burst using a bibliometric approach with VOSviewer and Citespace.

Results indicated that: overall, STEM education has increasingly gained scholarly attention and is developing diversely by emphasizing interdisciplinary, cross-domain and regional collaboration. In terms of global collaboration, a collaborative network with the USA in the center is gradually expanding to a global scope. In terms of research themes, four key topics can be outlined including educational equity, pedagogy, empirical effects and career development. Social, cultural and economic factors influence the way STEM education is implemented across different countries. The developed Western countries highlighted educational equity and disciplinary integration, while the developing countries tend to focus more on pedagogical practices. As for research trends, eastern countries are emphasizing humanistic leadership and cultural integration in STEM education; in terms of teachers’ professional development, teachers’ abilities of interdisciplinary integration, technology adoption and pedagogy application are of the greatest importance. With regards to pedagogy, the main focus is for developing students’ higher-order abilities. In terms of education equity, issues of gender and ethnicity were still the hottest topics, while the unbalanced development of STEM education across regions needs further research.

This study provides a global landscape of STEM education along the timeline, which illustrates the yearly progressive development of STEM education and indicates the future trends.

Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.

To overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.