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Article
Publication date: 27 December 2022

Ge Li, Qiushi Kang, Fanfan Niu and Chenxi Wang

Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s…

Abstract

Purpose

Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device.

Design/methodology/approach

In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated.

Findings

The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips.

Originality/value

To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.

Details

Microelectronics International, vol. 40 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 20 April 2023

Lezhi Ye, Xuanjie Song and Chang Yue

Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement…

83

Abstract

Purpose

Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment.

Design/methodology/approach

The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied.

Findings

The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency.

Originality/value

Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding.

Details

Microelectronics International, vol. 41 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

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