Search results

This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption.

The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects.

It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely.

In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions.

The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation.

This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

As the speed, density, power dissipation, and overall performance of semiconductor chips continue to improve, electronic equipment designers are finding that their ability to utilise new, high performance ICs is limited by the electrical performance, cost and turnaround time associated with the higher levels of packaging and interconnection. With the evolution of silicon foundries, CAD systems, logic array and standard cell technology, the designer now has the ability to develop and implement custom IC functions rapidly at a fraction of the cost and time associated with full custom IC development. The driving force for this evolution is the need for reduction of product development time and cost. As electronic product life cycles continue to decrease, so must the development time. Although the need to reduce component development times has been acted on first by the semiconductor manufacturers, suppliers of packaging and interconnection components are also feeling the need to provide customised designs rapidly and at low cost. Unilayer II is a discrete wire circuit board technology with a wiring density capability approximating that of multilayer printed wiring boards. However, since the wiring is defined in software and implemented on a numerically controlled wiring machine, the time and cost associated with development, and also with wiring changes, is greatly reduced. This paper presents the results of extensive electrical testing performed to characterise the electrical performance of the discrete wire Unilayer II transmission lines. Characteristic impedance, propagation velocity, capacitance, inductance, and crosstalk are discussed in detail.

This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.

An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, V_DD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.

The results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.

Considering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.

The design, fabrication and experimental validation of defected microstrip structure (DMS) are proposed to address the problem of near-end crosstalk (NEXT) and far-end crosstalk (FEXT) between the microstrip transmission lines in a printed circuit board.

The proposed DMS evolved with the combination of spur line (L-shaped DMS) and U-shaped DMS topologies. This technique reduces the strength of electromagnetic coupling and suppresses crosstalk by optimizing the capacitive and inductive coupling ratio between the linked microstrip lines. The practical inductance value is much more significant in DMS than in defected ground structures (DGS), but the capacitance value remains the same.

A DMS unit is etched on the aggressor microstrip line instead of the DGS circuit. Because there is no leakage via the ground plane and the circuit size is far smaller than with DGS, the enclosure issue is disregarded. DMS structures have a larger effective inductance and are resistant to electromagnetic interference. A tightly coupled transmission line structure with minimal separation between the coupled microstrip line is designed using DMS. Further research must be conducted to improve the NEXT, FEXT and spacing between the transmission lines.

Simulation and actual measurement results show that the proposed DMS structure can effectively suppress crosstalk by analysing the S-parameters, namely, S_12, S_13 and S_14, with measured values of 1.48 dB, 20.65 dB and 21.099 dB, respectively. The data rate is measured to be 1.34 Gbps as per the eye diagram characterization. The results show that the NEXT and FEXT are reduced by approximately 20 dB in the frequency range of 1–11 GHz for mixed signals. The substantial measured results in the vector network analyser coincide with the computer simulation technology microwave studio suite simulation results.

The purpose of this paper is to design a suitable guard trace to reduce the electromagentic interference between two closely spaced high frequency transmission lines. A novel cross-shaped resonator combined via fence is passed down to alleviate far-end and near-end crosstalk (NEXT) in tightly coupled high-speed transmission lines. The distance between the adjacent transmission lines is increased stepwise as a function of trace width.

A rectangular-shaped resonator via fence is connected by a guard trace has been proposed to overcome the coupling between the traces that is separated by 2 W. Similarly, by creating a cross-shaped resonator via fence connected by guard trace that reduces the spacing further by 1.5 W.

A tightly coupled transmission line structure that needs separation by a designed unit cell structure. Further research needs to be conducted to improve the NEXT, far-end crosstalk (FEXT) and spacing between the transmission lines.

This study portrays a novel method that combines the resonators via fence with a minimum spacing between the tightly coupled transmission lines which reduce the NEXT and FEXT; thereby reducing the size of the routing area. The resultant test structures are characterized at high frequencies using time domain and frequency domain analysis. The following scattering parameters such as insertion loss, NEXT and FEXT of the proposed method are measured as 1.504 dB, >30 dB and >20 dB, respectively.

To analyze the effect of voltage scaling on crosstalk.

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. V_A (input at aggressor node A) and V_B (input at victim node B) switching in same direction; V_A is switching and V_B at static low; V_A and V_B are switching in opposite direction; V_A is switching and V_B at static high.

It is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.

Voltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.

The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.

It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.

While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Fixed mode noise and random mode noise always exist in the image sensor, which affects the imaging quality of the image sensor. The charge diffusion and color mixing between pixels in the photoelectric conversion process belong to fixed mode noise. This study aims to improve the image sensor imaging quality by processing the fixed mode noise.

Through an iterative training of an ergoable long- and short-term memory recurrent neural network model, the authors obtain a neural network model able to compensate for image noise crosstalk. To overcome the lack of differences in the same color pixels on each template of the image sensor under flat-field light, the data before and after compensation were used as a new data set to further train the neural network iteratively.

The comparison of the images compensated by the two sets of neural network models shows that the gray value distribution is more concentrated and uniform. The middle and high frequency components in the spatial spectrum are all increased, indicating that the compensated image edges change faster and are more detailed (Hinton and Salakhutdinov, 2006; LeCun et al., 1998; Mohanty et al., 2016; Zang et al., 2023).

In this paper, the authors use the iterative learning color image pixel crosstalk compensation method to effectively alleviate the incomplete color mixing problem caused by the insufficient filter rate and the electric crosstalk problem caused by the lateral diffusion of the optical charge caused by the adjacent pixel potential trap.