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This paper aims to improve the life of the printed circuit boards (PCB) used in computers based on modal analysis by increasing the natural frequency of the PCB assembly.
Abstract
Purpose
This paper aims to improve the life of the printed circuit boards (PCB) used in computers based on modal analysis by increasing the natural frequency of the PCB assembly.
Design/methodology/approach
In this work, through experiments and numerical simulations, an attempt has been made to increase the fundamental natural frequency of the PCB assembly as high as practically achievable so as to minimize the impacts of dynamic loads acting on it. An optimization tool in the finite element software (ANSYS) was used to search the specified design space for the optimal support location of the six fastening screws.
Findings
It is observed that by changing the support locations based on the optimization results the fundamental natural frequency can be raised up to 51.1% and the same is validated experimentally.
Research limitations/implications
Manufacturers of PCBs used in computers fix the support locations based on symmetric feature of the board not on the dynamic behavior of the assembly. This work might lead manufacturers to redesign the location of other surface mount components.
Practical implications
This work provides guidelines for PCB manufacturers to finalize their support locating points which will improve the dynamic characteristics of the PCB assembly during its functioning.
Originality/value
This study provides a novel method to improve the life of PCB based on support locations optimization which includes majority of the surface mount components that contributes to the total mass the PCB assembly.
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Yangyang Lai and Seungbae Park
This paper aims to propose a method to quickly set the heating zone temperatures and conveyor speed of the reflow oven. This novel approach intensely eases the trial and error in…
Abstract
Purpose
This paper aims to propose a method to quickly set the heating zone temperatures and conveyor speed of the reflow oven. This novel approach intensely eases the trial and error in reflow profiling and is especially helpful when reflowing thick printed circuit boards (PCBs) with bulky components. Machine learning (ML) models can reduce the time required for profiling from at least half a day of trial and error to just 1 h.
Design/methodology/approach
A highly compact computational fluid dynamics (CFD) model was used to simulate the reflow process, exhibiting an error rate of less than 1.5%. Validated models were used to generate data for training regression models. By leveraging a set of experiment results, the unknown input factors (i.e. the heat capacities of the bulkiest component and PCB) can be determined inversely. The trained Gaussian process regression models are then used to perform virtual reflow optimization while allowing a 4°C tolerance for peak temperatures. Upon ensuring that the profiles are inside the safe zone, the corresponding reflow recipes can be implemented to set up the reflow oven.
Findings
ML algorithms can be used to interpolate sparse data and provide speedy responses to simulate the reflow profile. This proposed approach can effectively address optimization problems involving multiple factors.
Practical implications
The methodology used in this study can considerably reduce labor costs and time consumption associated with reflow profiling, which presently relies heavily on individual experience and skill. With the user interface and regression models used in this approach, reflow profiles can be swiftly simulated, facilitating iterative experiments and numerical modeling with great effectiveness. Smart reflow profiling has the potential to enhance quality control and increase throughput.
Originality/value
In this study, the employment of the ultimate compact CFD model eliminates the constraint of components’ configuration, as effective heat capacities are able to determine the temperature profiles of the component and PCB. The temperature profiles generated by the regression models are time-sequenced and in the same format as the CFD results. This approach considerably reduces the cost associated with training data, which is often a major challenge in the development of ML models.
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Maitri Mistry, Rahul Gupta, Swati Jain, Jaiprakash V. Verma and Daehan Won
The purpose of this paper is to develop a machine learning model that predicts the component self-alignment offsets along the length and width of the component and in the angular…
Abstract
Purpose
The purpose of this paper is to develop a machine learning model that predicts the component self-alignment offsets along the length and width of the component and in the angular direction. To find the best performing model, various algorithms like random forest regressor (RFR), support vector regressor (SVR), neural networks (NN), gradient boost (GB) and K-nearest neighbors (KNN) were performed and analyzed. The models were implemented using input features, which can be categorized as solder paste volume, paste-pad offset, component-pad offset, angular offset and orientation.
Design/methodology/approach
Surface-mount technology (SMT) is the technology behind the production of printed circuit boards, which is used in several types of commercial equipment such as communication devices, home appliances, medical imaging systems and sensors. In SMT, components undergo movement known as self-alignment during the reflow process. Although self-alignment is used to decrease the misalignment, it may not work for smaller size chipsets. If the solder paste depositions are not well-aligned, the self-alignment might deteriorate the final alignment of the component.
Findings
It were trained on their targets. Results obtained by each method for each target variable were compared to find the algorithm that gives the best performance. It was found that RFR gives the best performance in case of predicting offsets along the length and width of the component, whereas SVR does so in case of predicting offsets in the angular direction. The scope of this study can be extended to developing this model further to predict defects that can occur during the reflow process. It could also be developed to be used for optimizing the placement process in SMT.
Originality/value
This paper proposes a predictive model that predicts the component self-alignment offsets along the length and width of component and in the angular direction. To find the best performing model, various algorithms like RFR, SVR, NN, GB and KNN were performed and analyzed for predicting the component self-alignment offsets. This helps to achieve the following research objectives: best machine learning model for prediction of component self-alignment offsets. This model can be used to optimize the mounting process in SMT, which reduces occurrences of defects and making the process more efficient.
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Chun Hei Edmund Sek, M.Z. Abdullah, Kok Hwa Hwa Yu and Shaw Fong Wong
This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage…
Abstract
Purpose
This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.
Design/methodology/approach
This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.
Findings
Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.
Research limitations/implications
The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.
Practical implications
This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.
Social implications
The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.
Originality/value
The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.
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Soufyane Belhenini, Imad El Fatmi, Caroline Richard and Abdellah Tougui
This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is…
Abstract
Purpose
This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is based on the introduction of non-linear fracture mechanics in the numerical approach.
Design/methodology/approach
The integration of non-linear fracture mechanics into the numerical approach requires the proposal and validation of several simplifying assumptions. Initially, a dynamic 3D model was simplified to a dynamic 2D model. Subsequently, the dynamic 2D model is replaced with an equivalent static 2D model. The equivalent static 2D model was used to perform calculations considering the non-linear fracture mechanics. A crack was modelled in the critical bump. The J-integral was used as a comparative parameter to study the effects of crack length, crack position and chip thickness on the fracture toughness of the solder bump.
Findings
The different simplifying assumptions were validated by comparing the results obtained by the various models. Numerical results showed a high risk of failure at the critical solder bump in a zone close to the intermetallic layer. The obtained results were in agreement with the post-test observations using the “Dye and Pry” methods.
Originality/value
The originality of this study lies in the introduction of non-linear fracture mechanics to model the mechanical response of solder bumps during drop impact. This study led to some interesting conclusions, highlighting the advantage of introducing non-linear fracture mechanics into the numerical simulations of microelectronic components during a drop impact.
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Yokesh V., Gulam Nabi Alsath and Malathi Kanagasabai
The design, fabrication and experimental validation of defected microstrip structure (DMS) are proposed to address the problem of near-end crosstalk (NEXT) and far-end crosstalk…
Abstract
Purpose
The design, fabrication and experimental validation of defected microstrip structure (DMS) are proposed to address the problem of near-end crosstalk (NEXT) and far-end crosstalk (FEXT) between the microstrip transmission lines in a printed circuit board.
Design/methodology/approach
The proposed DMS evolved with the combination of spur line (L-shaped DMS) and U-shaped DMS topologies. This technique reduces the strength of electromagnetic coupling and suppresses crosstalk by optimizing the capacitive and inductive coupling ratio between the linked microstrip lines. The practical inductance value is much more significant in DMS than in defected ground structures (DGS), but the capacitance value remains the same.
Findings
A DMS unit is etched on the aggressor microstrip line instead of the DGS circuit. Because there is no leakage via the ground plane and the circuit size is far smaller than with DGS, the enclosure issue is disregarded. DMS structures have a larger effective inductance and are resistant to electromagnetic interference. A tightly coupled transmission line structure with minimal separation between the coupled microstrip line is designed using DMS. Further research must be conducted to improve the NEXT, FEXT and spacing between the transmission lines.
Originality/value
Simulation and actual measurement results show that the proposed DMS structure can effectively suppress crosstalk by analysing the S-parameters, namely, S_12, S_13 and S_14, with measured values of 1.48 dB, 20.65 dB and 21.099 dB, respectively. The data rate is measured to be 1.34 Gbps as per the eye diagram characterization. The results show that the NEXT and FEXT are reduced by approximately 20 dB in the frequency range of 1–11 GHz for mixed signals. The substantial measured results in the vector network analyser coincide with the computer simulation technology microwave studio suite simulation results.
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Hongyu Du, Rong Yang, Taochen Gu, Xiang Zhou, Samar Yazdani, Eric Sambatra, Fayu Wan, Sébastien Lallechere and Blaise Ravelo
The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study…
Abstract
Purpose
The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained.
Design/methodology/approach
The identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established.
Findings
This paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function.
Originality/value
The NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.
Details
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Xiao He, Lijuan Huang, Meizhen Xiao, Chengyong Yu, En Li and Weiheng Shao
The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the…
Abstract
Purpose
The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.
Design/methodology/approach
The approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.
Findings
To meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.
Originality/value
The PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.
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Paulina Araújo Capela, Maria Sabrina Souza, Sharlane Costa, Jose C. Teixeira, Miguel Fernandes, Hugo Figueiredo, Isabel Delgado and Delfim Soares
In a printed circuit board assembly (PCBA), the coefficient of thermal expansion (CTE) mismatch between the solder joint materials has a detrimental impact on reliability. The…
Abstract
Purpose
In a printed circuit board assembly (PCBA), the coefficient of thermal expansion (CTE) mismatch between the solder joint materials has a detrimental impact on reliability. The mechanical stresses caused by the thermal changes of the assembly lead to fatigue and sometimes the failure of the solder joints. The purpose of this study is to propose a novel pad design to obtain an interrupted solder/substrate interface, to improve the PCBA reliability.
Design/methodology/approach
An interruption in the continuous intermetallic compound (IMC) layer of a solder joint was implemented, by the deposition of a silicone film in the pad, changing its geometry. That change allows a redistribution of stresses in the most ductile zone of the solder joint, the solder. The stress concentration at the solder/substrate interface is reduced, as well as the general state of stress at the solder joint.
Findings
A new way was developed to reduce the stress on the solder joints, caused by thermal variations, because of the different components CTEs mismatch. This new method consists of interrupting the IMC layers of the solder joint, strategically, redirecting the usual stresses to a more ductile area of the joint, the solder. This is an innovative method that allows increase the lifetime of PCBAs and the equipments.
Originality/value
In this study, a new pad design concept for higher solder joint reliability was developed to reduce the shear stress in the solder joints because of the CTE mismatch between all the solder joint components.
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