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This paper aims to investigate the self-alignment of 0603 size (1.5 × 0.75 mm) chip resistors, which were soldered by infrared or vapour phase soldering. The results were used for establishing an artificial neural network for predicting the component movement during the soldering.

The components were soldered onto an FR4 testboard, which was designed to facilitate the measuring of the position of the components both prior to and after the soldering. A semi-automatic placement machine misplaced the components intentionally, and the self-alignment ability was determined for soldering techniques of both infrared and vapour phase soldering. An artificial neural network-based prediction method was established, which is able to predict the position of chip resistors after soldering as a function of component misplacement prior to soldering.

The results showed that the component can self-align from farer distances by using vapour phase method, even from relative misplacement of 50 per cent parallel to the shorter side of the component. Components can self-align from a relative misplacement only of 30 per cent by using infrared soldering method. The established artificial neural network can predict the component self-alignment with an approximately 10-20 per cent mean absolute error.

It was proven that the vapour phase soldering method is more stable from the component’s self-alignment point of view. Furthermore, machine learning-based predictors can be applied in the field of reflow soldering technology, and artificial neural networks can predict the component self-alignment with an appropriately low error.

The purpose of this paper is to develop a machine learning model that predicts the component self-alignment offsets along the length and width of the component and in the angular direction. To find the best performing model, various algorithms like random forest regressor (RFR), support vector regressor (SVR), neural networks (NN), gradient boost (GB) and K-nearest neighbors (KNN) were performed and analyzed. The models were implemented using input features, which can be categorized as solder paste volume, paste-pad offset, component-pad offset, angular offset and orientation.

Surface-mount technology (SMT) is the technology behind the production of printed circuit boards, which is used in several types of commercial equipment such as communication devices, home appliances, medical imaging systems and sensors. In SMT, components undergo movement known as self-alignment during the reflow process. Although self-alignment is used to decrease the misalignment, it may not work for smaller size chipsets. If the solder paste depositions are not well-aligned, the self-alignment might deteriorate the final alignment of the component.

It were trained on their targets. Results obtained by each method for each target variable were compared to find the algorithm that gives the best performance. It was found that RFR gives the best performance in case of predicting offsets along the length and width of the component, whereas SVR does so in case of predicting offsets in the angular direction. The scope of this study can be extended to developing this model further to predict defects that can occur during the reflow process. It could also be developed to be used for optimizing the placement process in SMT.

This paper proposes a predictive model that predicts the component self-alignment offsets along the length and width of component and in the angular direction. To find the best performing model, various algorithms like RFR, SVR, NN, GB and KNN were performed and analyzed for predicting the component self-alignment offsets. This helps to achieve the following research objectives: best machine learning model for prediction of component self-alignment offsets. This model can be used to optimize the mounting process in SMT, which reduces occurrences of defects and making the process more efficient.

The surface mount technology (SMT) assembly process for 0.4 mm pitch chip scale package (CSP) components was studied in this work. For the screen printing process, the printing performance of different solder pastes, aperture shapes and sizes was investigated. Square apertures and a fine particle size in the solder paste provided a better paste release. Besides optimising the printing process capability and minimizing the printing defects such as bridging and missing paste, the total volume of solder consisting of the paste and the solder ball has to be considered in order to maximize the final process yield. For the pick & place process, the accuracy required for the placement equipment was determined by studying the self‐alignment of the lead‐free CSPs (with Sn/4.0Ag/0.5Cu balls) during the reflow process using lead‐free Sn/3.9Ag/0.6Cu paste. The components were intentionally misplaced up to ∼50percent off‐pad. After reflow, x‐ray inspection showed that the components had aligned to the pad. By considering the stack‐up of the printed circuit board pad location and size tolerances, the solder paste printing tolerances and the placement tolerances, the required alignment accuracy for the pick & place equipment was established to meet the total process capability requirement.

Several effects of the atmosphere in the soldering oven on both the soldering process itself and the soldering results are discussed. Experiments have been undertaken to compare the results of soldering in air and in nitrogen containing 10,100 and 1000 ppm oxygen, in which, e.g., discolouration, wettability, solderability after reflow, solder bridging and solder‐ball formation were investigated. Unmounted FR‐4 testboards with both an RMA solder paste of known high quality and a low‐residue paste were used. Mounted test boards were used to analyse the self‐alignment of components and to compare the levels of soldering defects obtained in air and in nitrogen. The test results show that a nitrogen atmosphere containing 1000 ppm of oxygen or less is sufficiently pure to realise improved soldering conditions for most types of components. For the low‐residue paste tested, 1000 ppm is too high, but 100 ppm is sufficiently low. All effects on the soldering process will depend on the amount of oxygen in the gas. To produce an oven atmosphere of nitrogen with a very low amount of O2 (e.g., <100 ppm) is rather expensive, if this oven is to work under production conditions. Will the extra cost of investment and gas consumption be worthwhile in view of a better production yield and higher product quality? The authors explain why they do not believe this to be the case.

The electronics industry will implement lead‐free soldering in the near future. Lead‐free implementation steps are divided into lead‐free process and lead‐free product. The eutectic Sn/Ag/Cu alloy seems to have become the most widely used alloy in the implementation of lead‐free processes. In this study, the requirements for component placement are discussed from the lead‐free process point of view. Experiments concerning the self‐alignment capability and tack strength of both tin‐lead and lead‐free solder pastes are presented. According to the results, a bigger variation in self‐alignment capabilities can be expected when using a lead‐free paste. The paste properties affecting the self‐alignment mechanism and tack strength are also discussed.

This paper focuses on the reliability of the solder joint after the self-alignment phenomenon during reflow soldering. The aim of this study is to analyse the joint quality of the self-alignment assemblies of SnAg alloy solder joints with varying silver content.

The shear strength assessment was conducted in accordance with the JIS Z3 198-7 standard. The standard visual inspection of IPC-A-610G was also performed to inspect the self-alignment features of the solder joint samples. Statistical analysis was conducted to determine the probabilistic relationship of shear strength of the misalignment components.

The results from the mechanical reliability study indicate that there were decreasing trends in the shear strength value as misalignment offset increased. For shift mode configuration in the range of 0-300 µm, the resulting chip assembly inspection after the reflow process was in line with the IPC-A-610G standard. The statistical analysis shows that the solder type variation was insignificant to the shear strength of the chip resistor. The study concluded that the fracture occurred partially in the termination metallization at the lower part of the chip resistor. The copper content of the joint on that area shows that the crack occurred in the solder joint, and high silver content on the selected zone indicated that the fracture happened partially in the termination structure, as the termination structure of the lead-free chip resistor consists of an inner layer of silver and an outer layer of tin.

This study’s findings provide valuable guidelines and references to engineers and integrated circuit designers during the reflow soldering process in the microelectronics industry.

Studies on the effect of component misalignment on joint mechanical reliability are still limited, and studies on solder joint reliability involving the effect of differing contents of silver on varying chip component offset are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the potential industry.

This paper outlines some general aspects of materials and processes for reliable soldering of chip components and presents some new results on testing of wettability and leaching of thick films, thermal fatigue of solders and the reliability of solder joints on different thick film metallisations.

The ever present need for the miniaturization of electronic assemblies has driven the size of passive components to as small as the 01005 package size. However, the packaging standards for these components are still under development. The purpose of this work is to report results from experiments designed to establish optimum process parameters, pad sizes and component clearances for the surface mounting of 01005 passive components.

The experiments were designed using MODDE, an experimental design software tool, and were carried out with both 01005 capacitors and resistors. All the assembled components were examined under microscope and judged according to industrial workmanship standards.

It was found that a viable solder paste printing process for the assembly of 01005 components can be achieved with a 75 μm thick stencil. Type 5 solder paste achieved a similar printing performance to type 4. Under the experimental conditions used, the optimum pad dimensions for the 01005 capacitors were 210 μm length, 220 μm width, 160 μm separation and for the resistors were 190 μm length, 220 μm width, 160 μm separation. The smallest component clearance to reliably avoid bridging was found to be 100 μm. A high placement force of 3.5 N was found to cause cracking of 01005 resistors.

From this work, a surface mount process for 01005 passive components is established and it is concluded that electronics packaging density can be increased through the assembly of these small components. In the near future, the widespread use of them will definitely facilitate a further reduction in the size of electronic assemblies, especially in handheld and portable devices.

The International Electronic Components Show in Paris in November, 1983, provided the occasion for a very successful meeting of ISHM‐France which attracted 170 attendees. The following presentations were given:

The relentless drive towards greater complexity and interconnection density on silicon integrated circuit (SIC) devices is leading to a reappraisal of techniques for making electrical connections from the SIC to the next level of packaging. The techniques being examined include fine pitch Wire Bonding, Tape Automated Bonding (TAB) and Flip‐chip Solder Bonding. This latter technique forms the subject of this paper. The history of flip‐chip solder bonding technology is briefly reviewed and metallurgical, physical and mechanical aspects of the bonding process and of the resulting joints are discussed. The merits of the flip‐chip bonding process are indicated and applications examples presented. Particular attention is given to the fabrication of a novel pyroelectric‐SIC thermal imaging sensor using flip‐chip solder bonding.