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The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology.

Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type metal–oxide–semiconductor transistor and the transistor operating in the saturation region through the connection of the novel circuit structure makes a further improvement on the performance of the whole circuit.

This design is base on the 0.18?m process of BCD, and the new bandgap reference circuit is verified. The results show that the circuit design not only is simple and novel but also can effectively improve the performance of the circuit. Bandgap voltage reference is an important module in integrated circuits and electronic systems. To improve the stability and performance of the whole circuit, simple structure of the bandgap reference voltage source is essential for a chip.

This paper adopts a new circuit structure, which directly connects the two base voltages of the transistors with the resistor. And the transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of LDO regulator circuit, at last to realize the temperature control.

This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor.

Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths.

The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena.

The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM).

Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ.

It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit.

This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

This paper aims to study different possibilities for implementing easy-to-use and cost-effective micro-systems to detect and trace expelled gases from rotten food. The paper covers various radio-frequency identification (RFID) technologies and gas sensors as the two promoting feasibilities for the tracing of packaged food. Monitoring and maintaining quality and safety of food in transport and storage from producer to consumer are the most important concerns in food industry. Many toxin gases, even in parts per billion ranges, are produced from corrupted and rotten food and can endanger the consumers’ health. To overcome the issues, intelligent traceability of food products, specifically the packaged ones, in terms of temperature, humidity, atmospheric conditions, etc., has been paid attention to by many researchers.

Food poisoning is a serious problem that affects thousands of people every year. Poisoning food must be recognized early to prevent a serious health problem.

Contaminated food is usually detectable by odor. A small gas sensors and low-cost tailored to the type of food packaging and a communication device for transmitting alarm output to the consumer are key factors in achieving intelligent packaging.

Conducting polymer composite, intrinsically conducting polymer and metal oxide conductivity gas sensors, metal–oxide–semiconductor field-effect transistor (MOSFET) gas sensors offer excellent discrimination and lead the way for a new generation of “smart sensors” which will mould the future commercial markets for gas sensors.

Small size, low power consumption, short response time, wide operating temperature, high efficiency and small area are most important features of introduced system for using in package food.

The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.

A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.

Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.

Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.