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Article
Publication date: 12 July 2011

Galia Marinova and Dimitar Dimitrov

The paper aims to present a learning environment for optimal synthesis of voltage regulator circuits (LEOS‐VRC) using PSPICE simulator.

Abstract

Purpose

The paper aims to present a learning environment for optimal synthesis of voltage regulator circuits (LEOS‐VRC) using PSPICE simulator.

Design/methodology/approach

LEOS‐VRC supports a database with voltage regulator circuits edited as projects in PSPICE compatible format and a methodology for optimal synthesis. The methodology is based on the estimation of multiple voltage regulator circuits' realizations over a given specification, through comparative study in PSPICE, using a set of predefined specific electrical characteristics, which values are determined from simulation waveforms. LEOS‐VRC allows integrating the voltage regulator circuit in a power supply system through adding transformer, rectifier and control stages. Both linear and switch‐mode power supplies are considered.

Findings

The methodology and examples proposed illustrate the efficiency of LEOS‐VRC for teaching and self‐education in the area of power supply circuit design.

Research limitations/implications

In future LEOS‐VRC database will be enlarged with new voltage regulator circuit topologies and new controller circuits.

Practical implications

LEOS‐VRC is suitable for students in electronics and designers of power supply circuits.

Originality/value

With LEOS‐VRC students become familiar with multisolution synthesis. By analyzing the complex behaviour of the power supply system and applying comparative study and optimization criteria, they can make a motivated selection of an optimal voltage regulator design solution for a concrete application.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 30 no. 4
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 23 July 2020

Sandeep Garg and Tarun Kumar Gupta

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology…

Abstract

Purpose

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

Design/methodology/approach

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

Findings

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

Originality/value

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 2 May 2017

Jacek Klucznik, Zbigniew Lubosny, Krzysztof Dobrzynski, Stanislaw Czapp, Robert Kowalak, Robert Trebski and Stanislaw Pokora

The paper aims to discuss problems of power and energy losses in a double-circuit overhead transmission line. It was observed from energy meters’ readings, that in such a…

Abstract

Purpose

The paper aims to discuss problems of power and energy losses in a double-circuit overhead transmission line. It was observed from energy meters’ readings, that in such a line, active power losses can be measured as “negative”. The “negative” active power losses appear when the active power injected to the circuit is lower than the active power received at the circuit end. The purpose of this paper is to explain this phenomenon.

Design/methodology/approach

Theoretical considerations based on mathematical model of the transmission line of π-type confirming that effect are presented. Power losses related to series impedance of the line and to shunt admittance are calculated. The theoretical considerations are confirmed by measurements done on the real transmission line.

Findings

The calculations allow to indicate components of the active power losses, i.e. related to electromagnetic coupling among wires of a given circuit, related to electromagnetic coupling between circuits and related to shunt capacitance asymmetry. The authors indicate the influence of the line/wires geometry on the active power losses in a double-circuit overhead transmission line.

Originality/value

Explanation of the effect of “negative” active power losses’ measurement in a double-circuit overhead transmission line is provided in this paper.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 36 no. 3
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 April 2005

Rajeevan Chandel, S. Sarkar and R.P. Agarwal

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and…

Abstract

Purpose

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Design/methodology/approach

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Findings

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

Research limitations

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

Originality/value

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

Details

Microelectronics International, vol. 22 no. 1
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 10 June 2014

Jean Claude Mutiganda

This study aims to analyse the role of circuits of power in institutionalising competitive tendering in public sector organisations and effects on accountability among…

Abstract

Purpose

This study aims to analyse the role of circuits of power in institutionalising competitive tendering in public sector organisations and effects on accountability among public decision makers.

Design/methodology/approach

The study used intensive field research data based on interviews, meeting observations and document analysis in a city, referred to as Sunset City, in Finland from 2008 to 2013.

Findings

The relationship between institutionalisation of competitive tendering and accountability for total costs of public services depends on how public officials use management accounting and control systems to limit procurement risks and how political decision makers hold public officials to account. This study uses the concept of organisational outflanking within the circuits of power to analyse and explain the finding of ceremonial accountability.

Research limitations/implications

Empirical findings cannot be generalised to other situations, but the theoretical framework used in this study can be applied elsewhere.

Practical implications

It is advisable to avoid institutionalising macro-institutional market-based mechanisms, such as open competitive tendering in public health care organisations and municipalities in the EU, the consequences of which in terms of total costs, quality of services and accountability among organisational actors at local levels cannot be foreseen, minimised or controlled.

Originality/value

This study uses the framework of circuits of power to extend the Burns and Scapens institutional framework to accountability for using public funds in outsourcing services during the ongoing financial crisis.

Details

Qualitative Research in Accounting & Management, vol. 11 no. 2
Type: Research Article
ISSN: 1176-6093

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Article
Publication date: 21 May 2018

Maria Major, Ana Conceição and Stewart Clegg

The purpose of this paper is to demonstrate the role of power relations in initiating and blocking accounting change that involves increased “responsibilisation” and…

Abstract

Purpose

The purpose of this paper is to demonstrate the role of power relations in initiating and blocking accounting change that involves increased “responsibilisation” and “incentivisation”, and to understand how institutional entrepreneurship is steered by power strategies.

Design/methodology/approach

An in-depth case study was carried out between 2010 and 2015 in a cardiothoracic surgery service (CSS) where a responsibility centre was introduced.

Findings

Introducing a responsibility centre within a CSS led to a change process, despite pressures for stability. The institutionalisation of change was conditioned by entrepreneurship that flowed through three circuits of power. Strategies were adapted according to changes in exogenous environmental contingencies and alterations in the actors’ relationships.

Originality/value

The contributions of the paper are several: first, it demonstrates that the existing literature discussing the implementation of responsibility centres cannot be isolated from power issues; second, it expands understanding of the power dynamics and processes of institutional entrepreneurship when implementing accounting change; third, it shows how change introduced by exogenous political economic events structured organisational circuits of power and blocked the introduction of the change initiative.

Details

Accounting, Auditing & Accountability Journal, vol. 31 no. 4
Type: Research Article
ISSN: 0951-3574

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Article
Publication date: 14 August 2020

Vaithiyanathan D., Megha Singh Kurmi, Alok Kumar Mishra and Britto Pari J.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high…

Abstract

Purpose

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

Design/methodology/approach

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

Findings

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

Originality/value

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Details

World Journal of Engineering, vol. 17 no. 6
Type: Research Article
ISSN: 1708-5284

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Article
Publication date: 8 May 2018

Behnam Ghavami

Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical…

Abstract

Purpose

Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.

Design/methodology/approach

In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.

Findings

Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.

Originality/value

The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 37 no. 3
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 March 1989

J.R. Tyler and D.K. Andrade

Recent developments in microwave GaAs technology are yielding devices with higher power capabilities and increased levels of integration. The mechanical and thermal…

Abstract

Recent developments in microwave GaAs technology are yielding devices with higher power capabilities and increased levels of integration. The mechanical and thermal properties of GaAs and other microwave materials play a key role in the design and assembly of microwave power circuits. Thermal management is a critical element of microwave power circuit design. Thermal properties of microwave materials are discussed and compared with standard microelectronic materials. Material selection criteria are described. Assembly and packaging techniques also affect the overall performance of the GaAs power circuit. The high operating frequencies of microwave circuits make ordinary circuit elements, such as wire bonds and printed conductors, reactive. In addition, electrical performance criteria, such as high current or low impedance, create unique assembly demands. The successful development of a GaAs‐based microwave product is dependent on careful attention to the material properties and precise assembly methods. Techniques of automated assembly and processing are discussed, with ah eye towards maintaining high quality and reliability.

Details

Microelectronics International, vol. 6 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 12 October 2015

João Oliveira and Stewart Clegg

This paper aims to clarify a paradox in an organisation: in the past, formally powerful “central” actors confronted important limitations in their relations with formally…

Abstract

Purpose

This paper aims to clarify a paradox in an organisation: in the past, formally powerful “central” actors confronted important limitations in their relations with formally less powerful actors. However, three innovations – the financial accounting module of an enterprise resource planning (ERP) system, a corporate centre (CC) and a shared services centre (SSC) – substantially changed and re-centred network power relations. The authors adopt a critical discourse to explain this paradox, contributing to the emerging literature on SSCs and bridging the management control and power literatures.

Design/methodology/approach

An in-depth, processual, actor-network theory-inspired three-year case study of a large Portuguese manufacturer.

Findings

As the intertwined accounting-related innovations were (re)mobilised by actors, dynamically adjusting to unfolding repercussions, control and power effects emerged, enabling enhanced organisational steering.

Research limitations/implications

Based on a single case, this paper highlights effects of managerial technologies, in particular ERPs and SSCs, on control and power relations, and refines Clegg’s model for future research.

Practical implications

The transactional, low value-added activities typically performed by SSCs should not lead to underestimating their potentially profound organisational consequences. However, the surrounding socio-technical network is decisive for the emerging, inter-related repercussions.

Originality/value

This paper explains the relative capacity of actors to influence the practices and configuration of the organisational network structurally, fixing power relations within the socio-technical network through innovations in the accounting area, in particular ERPs and SSCs. By revising Clegg’s circuits of power framework, this paper contributes to understanding possibilities and limits of accounting techniques in management control procedures.

Details

Qualitative Research in Accounting & Management, vol. 12 no. 4
Type: Research Article
ISSN: 1176-6093

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