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Existing control circuits for piezoelectric energy harvesting (PEH) suffers from long startup time or high power consumption. This paper aims to design an ultra-low power control circuit that can harvest weak ambient vibrational energy on the order of several microwatts to power heavy loads such as wireless sensors.

A self-powered control circuit is proposed, functioning for very brief periods at the maximum power point, resulting in a low duty cycle. The circuit can start to function at low input power thresholds and can promptly achieve optimal operating conditions when cold-starting. The circuit is designed to be able to operate without stable DC power supply and powered by the piezoelectric transducers.

When using the series-synchronized switch harvesting on inductor circuit with a large 1 mF energy storage capacitor, the proposed circuit can perform 322% better than the standard energy harvesting circuit in terms of energy harvested. This control circuit can also achieve an ultra-low consumption of 0.3 µW, as well as capable of cold-starting with input power as low as 5.78 µW.

The intermittent control strategy proposed in this paper can drastically reduce power consumption of the control circuit. Without dedicated cold-start modules and DC auxiliary supply, the circuit can achieve optimal efficiency within one input cycle, if the input signal is larger than voltage threshold. The proposed control strategy is especially favorable for harvesting energy from natural vibrations and can be a promising solution for other PEH circuits as well.

This paper aims to propose an integrated protection scheme for converters of a low-power, low-cost photovoltaic system. Power electronic converters use a variety of methods to limit overload and fault current. The use of insulated and non-insulated sensors along with additional circuits to detect and limit fault current can cause current to be limited or completely cut off before damage to semiconductor devices. In addition, fuses that have slower performance are used as backup for any type of protection.

First, all the candidate points for protection are investigated. In this paper, after examining the performance of glass fuses as linear resistors, they are used as a current feedback element. A simple, isolated and reliable circuit for fault detection at various points of the system has been proposed that can be implemented and operated in single shot or auto-reclose operating mode.

The experimental results of this circuit on a dc/dc converter and an H-bridge inverter show that it can cut off all instantaneous short circuit errors in less than 50 µs and prevent damage to the semiconductor switch.

In low-cost and low-power converters, it is usually not cost-effective to use complex and expensive devices. For this reason, these converters are more vulnerable to faults. On the other hand, in complex systems such as photovoltaics, several converters are used simultaneously in different parts, and the occurrence of a fault in each of them causes the whole system to fail.

The paper aims to present a learning environment for optimal synthesis of voltage regulator circuits (LEOS‐VRC) using PSPICE simulator.

LEOS‐VRC supports a database with voltage regulator circuits edited as projects in PSPICE compatible format and a methodology for optimal synthesis. The methodology is based on the estimation of multiple voltage regulator circuits' realizations over a given specification, through comparative study in PSPICE, using a set of predefined specific electrical characteristics, which values are determined from simulation waveforms. LEOS‐VRC allows integrating the voltage regulator circuit in a power supply system through adding transformer, rectifier and control stages. Both linear and switch‐mode power supplies are considered.

The methodology and examples proposed illustrate the efficiency of LEOS‐VRC for teaching and self‐education in the area of power supply circuit design.

In future LEOS‐VRC database will be enlarged with new voltage regulator circuit topologies and new controller circuits.

LEOS‐VRC is suitable for students in electronics and designers of power supply circuits.

With LEOS‐VRC students become familiar with multisolution synthesis. By analyzing the complex behaviour of the power supply system and applying comparative study and optimization criteria, they can make a motivated selection of an optimal voltage regulator design solution for a concrete application.

The paper aims to discuss problems of power and energy losses in a double-circuit overhead transmission line. It was observed from energy meters’ readings, that in such a line, active power losses can be measured as “negative”. The “negative” active power losses appear when the active power injected to the circuit is lower than the active power received at the circuit end. The purpose of this paper is to explain this phenomenon.

Theoretical considerations based on mathematical model of the transmission line of π-type confirming that effect are presented. Power losses related to series impedance of the line and to shunt admittance are calculated. The theoretical considerations are confirmed by measurements done on the real transmission line.

The calculations allow to indicate components of the active power losses, i.e. related to electromagnetic coupling among wires of a given circuit, related to electromagnetic coupling between circuits and related to shunt capacitance asymmetry. The authors indicate the influence of the line/wires geometry on the active power losses in a double-circuit overhead transmission line.

Explanation of the effect of “negative” active power losses’ measurement in a double-circuit overhead transmission line is provided in this paper.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

This study aims to analyse the role of circuits of power in institutionalising competitive tendering in public sector organisations and effects on accountability among public decision makers.

The study used intensive field research data based on interviews, meeting observations and document analysis in a city, referred to as Sunset City, in Finland from 2008 to 2013.

The relationship between institutionalisation of competitive tendering and accountability for total costs of public services depends on how public officials use management accounting and control systems to limit procurement risks and how political decision makers hold public officials to account. This study uses the concept of organisational outflanking within the circuits of power to analyse and explain the finding of ceremonial accountability.

Empirical findings cannot be generalised to other situations, but the theoretical framework used in this study can be applied elsewhere.

It is advisable to avoid institutionalising macro-institutional market-based mechanisms, such as open competitive tendering in public health care organisations and municipalities in the EU, the consequences of which in terms of total costs, quality of services and accountability among organisational actors at local levels cannot be foreseen, minimised or controlled.

This study uses the framework of circuits of power to extend the Burns and Scapens institutional framework to accountability for using public funds in outsourcing services during the ongoing financial crisis.

The purpose of this paper is to demonstrate the role of power relations in initiating and blocking accounting change that involves increased “responsibilisation” and “incentivisation”, and to understand how institutional entrepreneurship is steered by power strategies.

An in-depth case study was carried out between 2010 and 2015 in a cardiothoracic surgery service (CSS) where a responsibility centre was introduced.

Introducing a responsibility centre within a CSS led to a change process, despite pressures for stability. The institutionalisation of change was conditioned by entrepreneurship that flowed through three circuits of power. Strategies were adapted according to changes in exogenous environmental contingencies and alterations in the actors’ relationships.

The contributions of the paper are several: first, it demonstrates that the existing literature discussing the implementation of responsibility centres cannot be isolated from power issues; second, it expands understanding of the power dynamics and processes of institutional entrepreneurship when implementing accounting change; third, it shows how change introduced by exogenous political economic events structured organisational circuits of power and blocked the introduction of the change initiative.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.