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Article
Publication date: 12 August 2021

Guoda Wang, Ping Li, Yumei Wen and Zhichun Luo

Existing control circuits for piezoelectric energy harvesting (PEH) suffers from long startup time or high power consumption. This paper aims to design an ultra-low power control…

Abstract

Purpose

Existing control circuits for piezoelectric energy harvesting (PEH) suffers from long startup time or high power consumption. This paper aims to design an ultra-low power control circuit that can harvest weak ambient vibrational energy on the order of several microwatts to power heavy loads such as wireless sensors.

Design/methodology/approach

A self-powered control circuit is proposed, functioning for very brief periods at the maximum power point, resulting in a low duty cycle. The circuit can start to function at low input power thresholds and can promptly achieve optimal operating conditions when cold-starting. The circuit is designed to be able to operate without stable DC power supply and powered by the piezoelectric transducers.

Findings

When using the series-synchronized switch harvesting on inductor circuit with a large 1 mF energy storage capacitor, the proposed circuit can perform 322% better than the standard energy harvesting circuit in terms of energy harvested. This control circuit can also achieve an ultra-low consumption of 0.3 µW, as well as capable of cold-starting with input power as low as 5.78 µW.

Originality/value

The intermittent control strategy proposed in this paper can drastically reduce power consumption of the control circuit. Without dedicated cold-start modules and DC auxiliary supply, the circuit can achieve optimal efficiency within one input cycle, if the input signal is larger than voltage threshold. The proposed control strategy is especially favorable for harvesting energy from natural vibrations and can be a promising solution for other PEH circuits as well.

Details

Circuit World, vol. 49 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Book part
Publication date: 2 October 2023

Rafael Galvão de Almeida and Harley Silva

This article delves into the contributions of Milton Santos (1926–2001) to the economic study of entrepreneurship. Santos made contributions to spatial economics, urbanization…

Abstract

This article delves into the contributions of Milton Santos (1926–2001) to the economic study of entrepreneurship. Santos made contributions to spatial economics, urbanization, and planning theories, being an important author to the field of regional and urban economics. His most famous idea is the “two circuits” of the urban economy. According to this approach, the urban economies in peripheral countries create two economic-urban circuits that are both distinct and connected. The superior circuit comes from the technological modernization and cultivates international relationships. High-value goods and networks and new technologies circulate through it. The inferior circuit works outside these networks. It consists of low-dimension activities from local populations. Santos elaborated this theory to understand urbanization in peripheral countries and to give voice to the ones left behind by the development process. He did not write directly on entrepreneurship. We argue, however, that his thoughts can be important to entrepreneurship studies. The entrepreneurship discourse, that had in Schumpeter one of its main sources, assumes that the entrepreneur has traits related to the superior circuit, such as access to resources and networks, which would not be available to entrepreneurs in the inferior circuit. We argue that Santos’ contributions can inform economic thought in entrepreneurship by calling attention to how literature can approach structural problems and contribute to making economics a more diverse discipline.

Details

Research in the History of Economic Thought and Methodology: Including a Selection of Papers Presented at the First History of Economics Diversity Caucus Conference
Type: Book
ISBN: 978-1-80455-982-6

Keywords

Article
Publication date: 7 September 2023

Esra Kandemir Beser

The purpose of this study is to create an extended equivalent circuit model for a compound DC motor, consisting completely of electrical parameters and quantities.

Abstract

Purpose

The purpose of this study is to create an extended equivalent circuit model for a compound DC motor, consisting completely of electrical parameters and quantities.

Design/methodology/approach

The dynamic model of the compound DC motor is obtained by establishing the voltage equations for the armature and excitation circuit and the mechanical equation for the mechanical part. The mechanical parameters in the dynamic model are converted into electrical parameters with an electrical circuit proposed for the mechanical part. By combining the armature and excitation circuits with the electrical circuit created for the mechanical part, the extended equivalent circuit model of the compound DC motor is obtained. Because the proposed extended equivalent model is completely an electrical circuit, simulations can be made in the circuit simulation programme. Simulations of the proposed compound DC motor circuit were carried out, and the accuracy of the proposed circuit was verified by performing experimental studies with an existing compound motor.

Findings

When comparing speed and current profiles in experiments and simulations, it is seen that compound DC motor can be modelled with the proposed equivalent circuit including completely electrical elements in a simulation programme for the circuits. The results show that the proposed equivalent circuit satisfies the dynamic model of the compound motor.

Originality/value

In DC machine models, armature and excitation circuits are given as an electrical circuit, and mechanical part of the machine is modelled by only mechanical equations. The originality of this study is converting the dynamic model of an electrical machine consisting of electrical and mechanical equations into a completely electrical circuit. With the proposed method, the dynamic model of many motors can be converted into a completely electrical circuit. In this way, motors can be simulated as an electrical circuit in simulation programmes for the circuits, and the dynamic behaviour of motors can be obtained.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering , vol. 42 no. 6
Type: Research Article
ISSN: 0332-1649

Keywords

Article
Publication date: 29 July 2022

Yumei Song, Jianzhang Hao, Changhao Dong, Xizheng Guo and Li Wang

This paper aims to study a multi-level reinjection current source converter (MLR-CSC) that adds attracting properties such as the self-commutation and pulse multiplication to the…

Abstract

Purpose

This paper aims to study a multi-level reinjection current source converter (MLR-CSC) that adds attracting properties such as the self-commutation and pulse multiplication to the thyristor converter, which is of great significance for increasing the device capacity and reducing current harmonics on the grid side. Particularly, designing advantageous driving methods of the reinjection circuit is a critical issue that impacts the harmonic reduction and operation reliability of the MLR-CSC.

Design/methodology/approach

To deal with the mentioned issue, this paper takes the five-level reinjection current source converter (FLR-CSC), which is a type of the MLR-CSC, as the research object. Then, a method that can fully use combinations of five-level reinjection switching functions based on the concept of decomposition and recombination is proposed. It is worthy to mention that the proposed method can be easily extended to other multi-level reinjection circuits. Moreover, the working principle of the three-phase bridge circuit based on semi-controlled thyristors in the FLR-CSC that can achieve the four-quadrant power conversion is analyzed in detail.

Findings

Finally, the simulation and experimental results of FLR-CSC verify the effectiveness of the proposed reinjection circuit driving method and the operating principle of four-quadrant power conversion in this paper.

Originality/value

The outstanding features of the proposed driving method for FLR-CSC in this paper include combinations of reinjection switching functions that are fully exploited through three simple steps and can be conveniently extended to other multi-level reinjection circuits.

Details

Microelectronics International, vol. 40 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 7 March 2023

Nour Mohammad Murad, Antonio Jaomiary, Samar Yazdani, Fayrouz Haddad, Mathieu Guerin, George Chan, Wenceslas Rahajandraibe and Sahbi Baccar

This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive…

Abstract

Purpose

This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor.

Design/methodology/approach

The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established.

Findings

After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation.

Originality/value

An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering , vol. 42 no. 6
Type: Research Article
ISSN: 0332-1649

Keywords

Article
Publication date: 7 December 2021

Sébastien Lalléchére, Jamel Nebhen, Yang Liu, George Chan, Glauco Fontgalland, Wenceslas Rahajandraibe, Fayu Wan and Blaise Ravelo

The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function.

Abstract

Purpose

The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function.

Design/methodology/approach

The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC).

Findings

From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC.

Originality/value

This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.

Article
Publication date: 12 April 2022

Jingbo Zhao, Yan Tao and Zhiming Sun

This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose…

131

Abstract

Purpose

This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.

Design/methodology/approach

This paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.

Findings

The short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.

Research limitations/implications

The dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.

Practical implications

The research results provide a reference for the design of protection system.

Originality/value

The key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

Details

Circuit World, vol. 49 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 18 August 2021

Hongyu Du, Rong Yang, Taochen Gu, Xiang Zhou, Samar Yazdani, Eric Sambatra, Fayu Wan, Sébastien Lallechere and Blaise Ravelo

The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study…

Abstract

Purpose

The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained.

Design/methodology/approach

The identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established.

Findings

This paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function.

Originality/value

The NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.

Article
Publication date: 13 September 2021

Jitendra B. Zalke, Sandeepkumar R. Pandey, Ruchir V. Nandanwar, Atharva Sandeep Pande and Pravin Balu Nikam

The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed…

Abstract

Purpose

The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications.

Design/methodology/approach

This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load.

Findings

The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting.

Originality/value

To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.

Details

Circuit World, vol. 49 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 29 March 2021

Roohie Kaushik, Jasdeep Kaur and Anushree

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating…

612

Abstract

Purpose

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.

Design/methodology/approach

This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.

Findings

The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.

Research limitations/implications

Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.

Practical implications

Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.

Social implications

BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.

Originality/value

FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Details

Circuit World, vol. 50 no. 1
Type: Research Article
ISSN: 0305-6120

Keywords

1 – 10 of over 1000