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This paper aims to obtain a symmetrical step-down topology with lower equivalent capacity and wider step-down range under the condition of the same output. Two new symmetrical step-down topologies of star-connected autotransformers are proposed in this paper. Taking the equivalent capacity as the main parameter, the obtained topologies are modeled and analyzed in detail.

This paper adopts the research methods of design, modeling, analysis and simulation verification. First, the star-connected autotransformer is redesigned according to the design objective of symmetrical step-down topology. In addition, the mathematical model of two topologies is established and a detailed theoretical analysis is carried out. Finally, the theoretical results are verified by simulation.

Two symmetrical star-connected autotransformer step-down topologies are designed, the winding configurations of the corresponding topology are presented, the step-down ranges of these three topologies are calculated and the influence of step-down ratio on the equivalent capacity of autotransformer are analyzed. Through analysis, the target step-down topologies are obtained when the step-down ratio is [1.1, 5.4] and [1.1, 1.9] respectively.

Because the selected research object is only a star-connected autotransformer, the research results may lack generality. Therefore, researchers are encouraged to further study the topologies of other autotransformers.

This paper includes the implications of the step-down ratio on the equivalent capacity of autotransformers and the configuration of transformer windings.

The topologies designed in this paper enable star-connected autotransformer in the 12-pulse rectifier to be applied in step-down circumstances rather than situations of harmonic reduction only. At the same time, this paper provides a way that can be used to redesign the autotransformer in other multi-pulse rectifier systems, so that those transformers can be used in voltage regulation.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Despite South Africa’s ailing electrical grid, substantial renewable energy (RE) integration is planned for the country. As grid-integrated RE affects all grids differently, this study aims to develop an adaptable grid code-guided renewable power plant (RPP) control real-time simulation testbed, tailored to South African grid code requirements to study grid-integrated RE’s behaviour concerning South Africa’s unique conditions.

The testbed is designed using MATLAB’s Simulink and live script environments, to create an adaptable model where grid, RPP and RPP guiding grid codes are tailorable. This model is integrated with OPAL-RT’s RT-LAB and brought to real-time simulation using OPAL-RT’s OP4510 simulator. Voltage, frequency and short-circuit event case studies are performed through which the testbed’s abilities and performance are assessed.

Case study results show the following. The testbed accurately represents grid code voltage and frequency requirements. RPP point of connection (POC) conditions are consistently recognized and tracked, according to which the testbed then operates simulated RPPs, validating its design. Short-circuit event simulations show the simulated wind farm supports POC conditions relative to short-circuit intensity by curtailing active power in favour of reactive power, in line with local grid code requirements.

To the best of the authors’ knowledge, this is the first design of an adaptable grid code-guided RPP control testbed, tailored to South African grid code requirements in line with which RPP behavioural and grid integration studies can be performed.

The purpose of this paper is to implement a closed loop regulated bidirectional DC to DC converter for an application in the electric power system of more electric aircraft. To provide a consistent power supply to all of the electronic loads in an aircraft at the desired voltage level, good efficiency and desired transient and steady-state response, a smart and affordable DC to DC converter architecture in closed loop mode is being designed and implemented.

The aircraft electric power system (EPS) uses a bidirectional half-bridge DC to DC converter to facilitate the electric power flow from the primary power source – an AC generator installed on the aircraft engine’s shaft – to the load as well as from the secondary power source – a lithium ion battery – to the load. Rechargeable lithium ion batteries are used because they allow the primary power source to continue recharging them whenever the aircraft engine is running smoothly and because, in the event that the aircraft engine becomes overloaded during takeoff or turbulence, the charged secondary power source can step in and supply the load.

A novel nonsingular terminal sliding mode voltage controller based on exponential reaching law is used to keep the load voltage constant under any of the aforementioned circumstances, and its performance is contrasted with a tuned PI controller on the basis of their respective transient and steady-state responses. The former gives a faster and better transient and steady-state response as compared to the latter.

This research gives a novel control scheme for incorporating an auxiliary power source, i.e. rechargeable battery, in more electric aircraft EPS. The battery is so implemented that it can get regeneratively charged when primary power supply is capable of handling an additional load, i.e. the battery. The charging and discharging of the battery is carried out in closed loop mode to ensure constant battery terminal voltage, constant battery current and constant load voltage as per the requirement. A novel sliding mode controller is used to improve transient and steady-state response of the system.

Traditional level inverter technology has drawbacks in the aspect of Total harmonic distortion (THD) and switching losses for higher frequencies. Due to these drawbacks, two-level inverters have become unprofitable for high-power applications. Multilevel inverters (MLIs) are used to enhance the output waveform characteristics (i.e. low THD) and to offer various inverter topologies and switching methods.

MLIs are upgraded versions of two-level inverters that offer more output levels in current and voltage waveforms while lowering the dv/dt and di/dt ratios. This paper aims to review and compare the different topologies of MLI used in high-power applications. Single and multisource MLI's working principal and switching states for each topology are demonstrated and compared. A Simulink model system integrated using detailed circuit simulations in developed in MATLAB®–Simulink program. In this system, a constant voltage source connected to MLI to feed asynchronous motor with squirrel cage rotor type is used to demonstrate the efficacy of the MLI under different varying speed and torque conditions.

MLI has presented better control and good range of system parameters than two-level inverter. It is suggested that the MLIs like cascade-five-level and NPC-five-level have shown low current harmonics of around 0.43% and 1.87%, respectively, compared to two-level inverter showing 5.82%.

This study is the first of its kind comparing the different topologies of single and multisource MLIs. This study suggests that the MLIs are more suitable for high-power applications.

The purpose of this paper is to propose a method that can calculate the transportation infrastructure network service capacity enhancement given by planned transportation infrastructure projects construction. Managers can sequence projects more rationally to maximize the construction effectiveness of infrastructure investments.

This paper designed a computational network simulation software to generate topological networks based on established rules. Based on the topological networks, the software simulated the movement path of users and calculated the average travel time. This software allows the adjustment of parameters to suit different research objectives. The average travel time is used as an evaluation index to determine the most appropriate construction sequence.

In this paper, the transportation infrastructure network of Sichuan Province in China was used to demonstrate this software. The average travel time of the existing transportation network in Sichuan Province was calculated as 211 min using this software. The high-speed railways from Leshan to Xichang and from Xichang to Yibin had the greatest influence on shortening the average travel time. This paper also measured the changes in the average travel time under two strategies: shortening the maximum and minimum priorities. All the transportation network optimisation plans for Sichuan Province will be somewhere between these two strategies.

The contribution of this research are three aspects: First, a complex network analysis method that can take into account the differences of node elements is proposed. Second, it provides an effective tool for decision makers to plan transportation infrastructure construction. Third, the construction sequence of transportation infrastructure development plan can effect the infrastructure investment effectiveness.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.