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The purpose of this paper is to develop a simple chaotic circuit. The circuit can be fabricated by less discrete electronic components, within which complex dynamical behaviors can be generated.

A second-order non-autonomous inductor-free chaotic circuit is presented, which is obtained by introducing a sinusoidal voltage stimulus into the classical Wien-bridge oscillator. The proposed circuit only has two dynamic elements, and its nonlinearity is realized by the saturation characteristic of the operational amplifier in the classical Wien-bridge oscillator. After that, its dynamical behaviors are revealed by means of bifurcation diagram, Lyapunov exponent and phase portrait and further confirmed using the 0-1 test method. Moreover, an analog circuit using less discrete electronic components is implemented, and its experimental results are measured to verify the numerical simulations.

The equilibrium point located in a line segment varies with time evolution, which leads to the occurrence of periodic, quasi-periodic and chaotic behaviors in the proposed circuit.

Unlike the previously published works, the significant values of the proposed circuit with simple topology are inductor-free realization and without extra nonlinearity, which make the circuit can be used as a paradigm for academic teaching and experimental illustraction for chaos.

To develop an OTA‐C‐based universal filter realizing all standard transfer functions viz low pass, high pass, band pass, notch and all pass without an inverting amplifier and with minimum component matching condition.

By developing different sets of current and voltage relationship involving simple independent transconductance in biquadratic functions using three operational transconductance amplifiers the aim has been achieved.

The circuit produces all pass transfer function as stated above without inverting amplifier as has been used in most of the earlier circuits. All realizations except all pass filter requires no matching condition. The circuit remains stable for non‐ideal OTAs.

The proposed circuit finds wide utility in industrial and research applications as a signal processing element.

The purpose of this paper is to develop two types of simple jerk circuits and to carry out their dynamical analyses using a unified mathematical model.

Two types of simple jerk circuits only involve a nonlinear resistive feedback channel composited by a nonlinear device and an inverter. The nonlinear device is implemented through parallelly connecting two diode-switch-based series branches. According to the classifications of switch states and circuit types, a unified mathematical model is established for these two types of simple jerk circuits, and the origin symmetry and scale proportionality along with the origin equilibrium stability are thereby discussed. The coexisting bifurcation behaviors in the two types of simple jerk systems are revealed by bifurcation plots, and the origin symmetry and scale proportionality are effectively demonstrated by phase plots and attraction basins. Moreover, hardware experimental measurements are performed, from which the captured results well validate the numerical simulations.

Two types of simple jerk circuits are unified through parallelly connecting two diode-switch-based series branches and a unified mathematical model with six kinds of nonlinearities is established. Especially, the origin symmetry and scale proportionality for the two types of simple jerk systems are discussed quantitatively. These jerk circuits are all simple and inexpensive, easy to be physically implemented, which are helpful to explore chaos-based engineering applications.

Unlike previous works, the significant values are that through unifying these two types of simple jerk systems, a unified mathematical model with six kinds of nonlinearities is established, upon which symmetrically scaled coexisting behaviors are numerically disclosed and experimentally demonstrated.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

The purpose of this paper is to introduce an approach for m‐valued classical and non‐classical (reversible and quantum) optical computing. The developed approach utilizes new multiplexer‐based optical devices and circuits within switch logic to perform the required optical computing. The implementation of the new optical devices and circuits in the optical regular logic synthesis using new lattice and systolic architectures is introduced, and the extensions to quantum optical computing are also presented.

The new linear optical circuits and systems utilize coherent light beams to perform the functionality of the basic logic multiplexer. The 2‐to‐1 multiplexer is a basic building block in switch logic, where in switch logic a logic circuit is implemented as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less‐costly in synthesizing wide variety of logic circuits and systems. The extensions to quantum optical computing using photon spins and the collision of Manakov solitons are also presented.

New circuits for the optical realizations of m‐valued classical and reversible logic functions are introduced. Optical computing extensions to linear quantum computing using photon spins and nonlinear quantum computing using Manakov solitons are also presented. Three new multiplexer‐based linear optical devices are introduced that utilize the properties of frequency, polarization and incident angle that are associated with any light‐matter interaction. The hierarchical implementation of the new optical primitives is used to synthesize regular optical reversible circuits such as the m‐valued regular optical reversible lattice and systolic circuits. The concept of parallel optical processing of an array of input laser beams using the new multiplexer‐based optical devices is also introduced. The design of regular quantum optical systems using regular quantum lattice and systolic circuits is introduced. New graph‐based quantum optical representations using various types of quantum decision trees are also presented to efficiently represent quantum optical circuits and systems.

The introduced methods for classical and non‐classical (reversible and quantum) optical regular circuits and systems are new and interesting for the design of several future technologies that require optimal design specifications such as super‐high speed, minimum power consumption and minimum size such as in quantum computing and nanotechnology.

To synthesize equivalent circuit obtained from reduced order model of large scale inductive PEEC circuits.

This paper describes an original approach for reducing and synthesizing large parasitic RLM electrical circuits coming from inductive Partial Element Equivalent Circuit (PEEC) models. The proposed technique enables the re-use of the reduced order model in the time domain circuit simulation context.

The paper shows how to use a synthesis method to realize an equivalent circuit issued from compressed PEEC circuits.

The coupling between methods PEEC and a compressed method as Fast Multipole Method (FMM) in order to reduce time and space consuming are well-known. The innovation here is to realise a smaller circuit equivalent with the original large scale PEEC circuits to use in temporal simulation tools. Moreover, this synthesis method reduces time and memories for modelling industrial application while maintaining high accuracy.

The paper aims to present a learning environment for optimal synthesis of voltage regulator circuits (LEOS‐VRC) using PSPICE simulator.

LEOS‐VRC supports a database with voltage regulator circuits edited as projects in PSPICE compatible format and a methodology for optimal synthesis. The methodology is based on the estimation of multiple voltage regulator circuits' realizations over a given specification, through comparative study in PSPICE, using a set of predefined specific electrical characteristics, which values are determined from simulation waveforms. LEOS‐VRC allows integrating the voltage regulator circuit in a power supply system through adding transformer, rectifier and control stages. Both linear and switch‐mode power supplies are considered.

The methodology and examples proposed illustrate the efficiency of LEOS‐VRC for teaching and self‐education in the area of power supply circuit design.

In future LEOS‐VRC database will be enlarged with new voltage regulator circuit topologies and new controller circuits.

LEOS‐VRC is suitable for students in electronics and designers of power supply circuits.

With LEOS‐VRC students become familiar with multisolution synthesis. By analyzing the complex behaviour of the power supply system and applying comparative study and optimization criteria, they can make a motivated selection of an optimal voltage regulator design solution for a concrete application.

This paper aims to discuss the relationship between the continued fraction form of the analytical solution in the frequency domain, the orthogonal function expansion and their circuit realization to derive an efficient representation of the eddy-current field in the conducting sheet and wire/cylinder. Effective frequency ranges of representations are analytically derived.

The Cauer circuit representation is derived from the continued fraction form of analytical solution and from the orthogonal polynomial expansion. Simple circuit calculations give the upper frequency bounds where the truncated circuit and orthogonal expansion are applicable.

The Cauer circuit representation and the orthogonal polynomial expansions for the magnetic sheet in the E-mode and for the wire in the axial H-mode are derived. The upper frequency bound for the Cauer circuit is roughly proportional to N⁴ with N inductive elements, whereas the frequency bound for the finite element eddy-current analysis with uniform N elements is roughly proportional to N².

The Cauer circuit representation is expected to provide an efficient homogenization method because it requires only several elements to describe the eddy-current field over a wide frequency range.

The applicable frequency ranges are analytically derived depending on the conductor geometry and on the truncation types.

Lack of optimization and improvement on experimental circuits precludes comprehensive statements. It is a deficiency of the existing chaotic circuit technology. One of the aims of this paper is to solve the above mentioned problems. Another purpose of this paper is to construct a 10 + 4-type chaotic secure communication circuit based on the proposed third-order 4 + 2-type circuit which can output chaotic phase portraits with high accuracy and high stability.

In Section 2 of this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new third-order Lorenz-like chaotic system is proposed based on the 4 + 2 circuit. Then some simulations are presented to verify that the proposed system is chaotic by using Multisim software. In Section 3, a fourth-order chaotic circuit is proposed on the basis of the third-order 4 + 2 chaotic circuit. In Section 4, the circuit design method of this paper is applied to chaotic synchronization and secure communication. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. In Section 5, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented in an analog electronic circuit. The analog circuit implementation results match the Multisim results.

The simulation results show that the proposed fourth-order chaotic circuit can output six phase portraits, and it can output a stable fourth-order double-vortex chaotic signal. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. The scheme has the advantages of clear thinking, efficient and high practicability. The experimental results show that the precision is improved by 2-3 orders of magnitude. Signal-to-noise ratio meets the requirements of engineering design. It provides certain theoretical and technical bases for the realization of a large-scale integrated circuit with a memristor. The proposed circuit design method can also be used in other chaotic systems.

In this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new chaotic system is proposed on the basis of the 4 + 2 chaotic circuit for the first time. Some simulations are presented to verify its chaotic characteristics by Multisim. Then the novel third-order 4 + 2 chaotic circuit is applied to construct a fourth-order chaotic circuit. Simulation results verify the existence of the new fourth-order chaotic system. Moreover, a new 10 + 4-type chaotic secure communication circuit is proposed based on chaotic synchronization of the novel third-order 4 + 2 circuit. To illustrate the effectiveness of the proposed scheme, the intensity limit and stability of the transmitted signal, the characteristic of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. Finally, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented through an analog electronic circuit, which are characterized by their high accuracy and good robustness. The analog circuit implementation results match the Multisim results.

New approaches for non‐classical neural‐based computing are introduced. The developed approaches utilize new concepts in three‐dimensionality, invertibility and reversibility to perform the required neural computing. The various implementations of the new neural circuits using the introduced paradigms and architectures are presented, several applications are shown, and the extension for the utilization in neural‐systolic computing is also introduced.

The new neural paradigms utilize new findings in computational intelligence and advanced logic synthesis to perform the functionality of the basic neural network (NN). This includes the techniques of three‐dimensionality, invertibility and reversibility. The extension of implementation to neural‐systolic computing using the introduced reversible neural‐systolic architecture is also presented.

Novel NN paradigms are introduced in this paper. New 3D paradigm of NL circuits called three‐dimensional inverted neural logic (3DINL) circuits is introduced. The new 3D architecture inverts the inputs and weights in the standard neural architecture: inputs become bases on internal interconnects, and weights become leaves of the network. New reversible neural network (RevNN) architecture is also introduced, and a RevNN paradigm using supervised learning is presented. The applications of RevNN to multiple‐output feedforward discrete plant control and to reversible neural‐systolic computing are also shown. Reversible neural paradigm that includes reversible neural architecture utilizing the extended mapping technique with an application to the reversible solution of the maze problem using the reversible counterpropagation NN is introduced, and new neural paradigm of reversibility in both architecture and training using reversibility in independent component analysis is also presented.

Since the new 3D NNs can be useful as a possible optimal design choice for compacting a learning (trainable) circuit in 3D space, and because reversibility is essential in the minimal‐power computing as the reduction of power consumption is a main requirement for the circuit synthesis of several emerging technologies, the introduced methods for non‐classical neural computation are new and interesting for the design of several future technologies that require optimal design specifications such as three‐dimensionality, regularity, super‐high speed, minimum power consumption and minimum size such as in low‐power control, adiabatic signal processing, quantum computing, and nanotechnology.