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The purpose of this paper is to design a voltage reference circuit for current source of radio frequency integrated circuit blocks. The voltage reference circuit is called voltage for current source (VCS).

The circuit concept is discussed. A voltage‐controlled oscillator (VCO) and buffer circuit together with VCS circuit are built to prove the concept. Though the VCS circuit employs no array of diode like standard bandgap circuit, it still employs the concept of proportional to absolute temperature (PTAT) and a complement to absolute temperature (CTAT) elements. The integrated VCO, together with VCO core and VCO buffer circuits, are designed for W‐CDMA application particularly for the demodulator section. All circuits are built in f_T=45 GHz SiGe BiCMOS process.

At 760 MHz the power consumption for core circuit is 0.6 and 3.3 mA for VCO buffer amplifier. The fabricated VCO circuit together with VCO buffer was tested and measured with VCO output of −6 dBm at 760 MHz with variation of 0.1 dBm across −40°C to 85°C.

A voltage reference circuit which is derived from PTAT and CTAT current generators is presented. The circuit is capable of providing a constant current across absolute temperature or a current PTAT.

Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

This paper aims to propose an integrated protection scheme for converters of a low-power, low-cost photovoltaic system. Power electronic converters use a variety of methods to limit overload and fault current. The use of insulated and non-insulated sensors along with additional circuits to detect and limit fault current can cause current to be limited or completely cut off before damage to semiconductor devices. In addition, fuses that have slower performance are used as backup for any type of protection.

First, all the candidate points for protection are investigated. In this paper, after examining the performance of glass fuses as linear resistors, they are used as a current feedback element. A simple, isolated and reliable circuit for fault detection at various points of the system has been proposed that can be implemented and operated in single shot or auto-reclose operating mode.

The experimental results of this circuit on a dc/dc converter and an H-bridge inverter show that it can cut off all instantaneous short circuit errors in less than 50 µs and prevent damage to the semiconductor switch.

In low-cost and low-power converters, it is usually not cost-effective to use complex and expensive devices. For this reason, these converters are more vulnerable to faults. On the other hand, in complex systems such as photovoltaics, several converters are used simultaneously in different parts, and the occurrence of a fault in each of them causes the whole system to fail.

As an initial step to implement total quality management (TQM) in a small manufacturing enterprise (SME) of electrical products, we applied statistical techniques to quantify and evaluate the data collected in order to improve the quality characteristics of a selected product circuit breaker. A circuit breaker will “jump” or the current will be cut short if a current stronger than 15A passes through the equipment. The time required for the circuit breaker to stop the flow of the current is called the trip‐time. Our major concern is to find out how sensitive a 15A circuit breaker is, and how reliable is the device. We were able to confirm several dominant factors that influence the trip‐time of the circuit breaker after conducting several experiments. We used regression analysis to find out the model that best fits the relationship between the current supply and the trip‐time of the 15A circuit breaker. Meanwhile reliability testings of the circuit breaker were performed. Balanced factorial design techniques were applied in finding out the optimal combination of factors with the highest success rate of trips. The results demonstrated that the optimal combination of factors we found could bring about quality improvement of the product.

This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.

This paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.

The short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.

The dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.

The research results provide a reference for the design of protection system.

The key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

This paper aims to improve the general circuit of driving and protection based on insulated gate bipolar transistor (IGBT) in dielectric barrier discharge power supply by designing a novel half-bridge inverter circuit with discrete components.

With one SG3524 chip, the structure based on discrete components is used to design the IGBT drive circuit. The driving waveform is isolated and sent out by photo-coupler 6N137. The protection circuit is realized by Hall sensor directly detecting the main circuit current, supplemented by a few components, including diodes, resistors, capacitors and triodes. It improves the reliability of the protection circuit.

In the driving circuit, the phase difference of signals from two channels are 180°. Moreover, when the duty cycle is set at 40%, it can ensure sufficient pulse width modulation response time. In the protection circuit, when over-current occurs, an intermittent output signal is automatically sent out. Furthermore, the over-current response time can be controlled independently. The peak voltage can be adjusted continuously from 0 to 30 kV with its frequency from 8 to 25 kHz and the power output up to 150 W.

The novel circuit of driving and protection makes not only its structure simpler and easier to be realized but also key parameters, such as frequency, the duty cycle and the driving voltage, continuously adjustable. Moreover, the power supply is suitable for other discharges such as corona discharge and jet discharge.

The theoretical method of converting the magnetic circuit into an electric circuit is mature, but the way to determine the inductances in the electric circuit is not reliable, especially for the core working in saturation status, and it is impossible to determine the inductances by the transformer terminal measurements, as the measurement information is not enough to determine a number of inductances. This paper aims to propose an approach of calculating the reluctances.

In this paper, an approach of calculating the reluctances is proposed based on the numerical simulation of magnetic field in transformer with different values of current excitation. The reluctance of a core segment or air region as a branch of magnetic circuit is obtained by the magnetic energy and magnetic flux. By this way, all the reluctances as function of flux can be determined, and then the inductances can be determined. The reluctances and equivalent electric circuit of three-phase integrative transformer is determined, and its validation is proved in the paper.

The single phase example shows that the proposed method has a good performances on analysis of the inrush current in deep saturation. The peak value of the inrush current derived from the proposed approach matches well with the results obtained by coupled circuit-FEM analysis, and the difference is about 4.8 per cent. For studies on dual models of single phase transformers, the leakage inductances have important effects on the peak value of the inrush current. The reluctances of three-phase transformer are calculated, and the equivalent circuit simulation results are slightly smaller than the coupled circuit-FEM simulation results.

Approach of calculating the reluctances based on the numerical simulation of magnetic field in transformer is proposed. The magnetic core and air space are divided into several segments, and the reluctance for each segment is calculated based on the energy in the region and the flux of the cross-sectional area. By applying various excitation currents, all the reluctances as function of flux can be determined, and then all the non-linear inductances including the non-linear leakage inductances are obtained. The proposed approach is reliable to determine a number of inductances in the dual electric circuit, especially for deep saturation status.

This paper aims to give a perspective about the variety of techniques which are available and are being further developed in the area of coupled field formulations, with selective bibliography and practical examples, to help postgraduate students, researchers and designers working in design or analysis of electrical machinery.

This paper reviews the recent trends in coupled field formulations. The use of these formulations for designing and non‐destructive testing of electrical machinery is described, followed by their classifications, solutions and applications. Their advantages and shortcomings are discussed.

The paper gives an overview of research, development and applications of coupled field formulations for electrical machinery based on more than 160 references. All landmark papers are classified. Practical engineering case studies are given which illustrate wide applicability of coupled field formulations.

Problems which continue to pose challenges to researchers are enumerated and the advantages of using the coupled‐field formulation are pointed out.

This paper gives a detailed description of the application of the coupled field formulation method to the analysis of problems that are present in different electrical machines. Examples of analysis of generators and transformers with this formulation are presented. The application examples give guidelines for its use in other analyses.

The coupled‐field formulation is used in the analysis of rotational machines and transformers where reference data are available and comparisons with other methods are performed and the advantages are justified. This paper serves as a guide for the ongoing research on coupled problems in electrical machinery.

The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.