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This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor.

The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established.

After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation.

An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different strategies of optimization and determines the problem of searching of the best strategy in sense of minimal computer time. The determining of the best strategy of optimization and a searching of possible structure of this strategy with a minimal computer time is a principal aim of this work.

Different kinds of strategies for circuit optimization have been evaluated from the point of view of operations’ number. The generalized methodology for the optimization of analog circuit was formulated by means of the optimum control theory. The main equations for this methodology were elaborated. These equations include the special control functions that are introduced artificially. This approach generalizes the problem and generates an infinite number of different strategies of optimization. A problem of construction of the best algorithm of optimization is defined as a typical problem of the control theory. Numerical results show the possibility of application of this approach for optimization of electronic circuits and demonstrate the efficiency and perspective of the proposed methodology.

Examples show that the better optimization strategies that are appeared in limits of developed approach have a significant time gain with respect to the traditional strategy. The time gain increases when the size and the complexity of the optimized circuit are increasing. An additional acceleration effect was used to improve the properties of presented optimization process.

The obtained results show the perspectives of new approach for circuit optimization. A large set of various strategies of circuit optimization serves as a basis for searching the better strategies with a minimum computer time. The gain in processor time for the best strategy reaches till several thousands in comparison with traditional approach.

This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.

This paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.

The short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.

The dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.

The research results provide a reference for the design of protection system.

The key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

A program for numerical simulation of two‐dimensional semiconductor devices coupled with an external circuit is described. The circuit equations are formulated using modified nodal analysis to allow an arbitrary configuration of elements like, e.g., also semiconductor compact models. Coupling to the numerical devices is attained via their admittance matrix leading to a two‐level Newton method. To calculate this matrix two methods are compared: (a) a linearization scheme and (b) a secant method. The comparison shows a significant speed advantage of the secant method despite its lower rate of convergence. The linearization scheme, however, is the more stable and robust method and should be used in critical cases where convergence problems can occur. An efficient bypassing scheme was developed for the linearization scheme leading to a computation speed comparable to that of the secant method, but maintaining the better convergence properties. A further advantage of the two‐level Newton method used in this work is that the CPU‐time consuming solution for the numerical devices can be done in parallel on different processors. Several examples are given to demonstrate the capabilities of the developed simulator.

The purpose of this study is to show that the humidity levels for surface insulation resistance (SIR)-related failures are dependent on the type of activators used in no-clean flux systems and to demonstrate the possibility of simulating the effects of humidity and contamination on printed circuit board components and sensitive parts if typical SIR data connected to a particular climatic condition are available. This is shown on representative components and typical circuits.

A range of SIR values obtained on SIR patterns with 1,476 squares was used as input data for the circuit analysis. The SIR data were compared to the surface resistance values observable on a real device printed circuit board assembly. SIR issues at the component and circuit levels were analysed on the basis of parasitic circuit effects owing to the formation of a water layer as an electrical conduction medium.

This paper provides a summary of the effects of contamination with various weak organic acids representing the active components in no-clean solder flux residue, and demonstrates the effect of humidity and contamination on the possible malfunctions and errors in electronic circuits. The effect of contamination and humidity is expressed as drift from the nominal resistance values of the resistors, self-discharge of the capacitors and the errors in the circuits due to parasitic leakage currents (reduction of SIR).

The methodology of the analysis of the circuits using a range of empirical leakage resistance values combined with the knowledge of the humidity and contamination profile of the electronics can be used for the robust design of a device, which is also important for electronic products relying on low current consumption for long battery lifetime.

Examples provide a basic link between the combined effect of humidity and contamination and the performance of electronic circuits. The methodology shown provides the possibility of addressing the climatic reliability of an electronic device at the early stage of device design by using typical SIR data representing the possible climate exposure.

The purpose of this paper is to develop a linearized equivalent electrical circuit of a photovoltaic generator. This circuit is appropriate to confront problems such as numerical instability, increased computational time and nonlinear/non‐canonical form of system equations that arise when a photovoltaic system is modelled, either with differential equations or with equivalent resistive circuits that are generated by electromagnetic transient software packages for power systems studies.

The proposed technique is based on nonlinear and well‐tested i_pv−v_pv equations which are however used in an alternative mathematical manner. The application of the Newton‐Raphson algorithm on the i_pv−v_pv equations leads to uncoupling of the i_pv and v_pv quantities in each time step of a digital simulation. This uncoupling is represented by a linearized equivalent electrical circuit.

The application of nodal analysis equivalent resistive circuits using the proposed equivalent photovoltaic generator circuit leads to a system model based on linear algebraic equations. This is in opposition to the nonlinear models that normally result when a nonlinear i_pv−v_pv equation is used. In addition, using the proposed scheme, the regular systematic methods of circuit analysis are fully capable of deriving the differential equations of a photovoltaic system in standard form, thus avoiding the time‐consuming solution process of nonlinear models.

In this paper, a new method of using the i_pv−v_pv characteristic equations is proposed which remarkably simplifies photovoltaic systems modeling. Moreover, a very important practical application is that by using this methodology one can develop a photovoltaic generator element in electromagnetic transient programs for power systems analysis, of great value to power engineers who are involved in photovoltaic systems modeling.

The purpose of this paper is to review cotemporary maintenance programs and analyze factory production data for an SF₆ gas filled circuit breaker population. Various maintenance techniques and studies are reviewed to understand the reliability of circuit breaker models and the impact manufacturing can have on long term maintenance considerations.

Production and field event data were analyzed using statistical analysis tools. The population data were formatted so that a recurrent event analysis could be conducted to establish the mean cumulative function (MCF) by model and product family (class). Average Field Two‐year Recorded Event Rate (AFTRER) is introduced and compared to commonly used Field Incident Rate (FIR) and Mean‐Time between Failure (MTBF) measures.

Common managerial operating questions can be answered as exhibited for the provided circuit breaker population. This includes the longevity of field issues, the anticipated life cycle of a model or class, and AFTRER for models or classes of interest. These statistical analysis tools are used to make critical production quality and asset management observations and aid in decision‐making.

Due to limitations in existing database systems, the cost of events and explanatory variables related to event rates were not included in the analyses. There remains much work to be done in terms of the installation and retro‐fitting of breakers with conditions monitors in the field.

A framework to analyze maintenance data from fleet of similar assets using recurrent event data analysis is provided. The methods illustrated here would be useful for quality and asset managers to make operating decisions. This includes resource allocation decisions across a network of equipment.

Data analyzed are for power circuit breakers which are a critical element in the operation and reliability of the US power grid.

Using recurrent event data analysis to review and develop solutions to production quality and asset management problems including a comparison of AFTRER to FIR and MTBF measures.

The purpose of this paper is to present the analyses of electrical circuits with arbitrary source terms defined on middle b cantor set by means of nonlocal fractal calculus and to evaluate the appropriateness of such unconventional calculus.

The nonlocal fractal integro-differential equations describing RL, RC, LC and RLC circuits with arbitrary source terms defined on middle b cantor set have been formulated and solved by means of fractal Laplace transformation. Numerical simulations based on the derived solutions have been performed where an LC circuit has been studied by means of Lagrangian and Hamiltonian formalisms. The nonlocal fractal calculus-based Lagrangian and Hamiltonian equations have been derived and the local fractal calculus-based ones have been revisited.

The author has found that the LC circuit defined on a middle b cantor set become a physically unsound system due to the unreasonable associated Hamiltonian unless the local fractal calculus has been applied instead.

For the first time, the nonlocal fractal calculus-based analyses of electrical circuits with arbitrary source terms have been performed where those circuits with order higher than 1 have also been analyzed. For the first time, the nonlocal fractal calculus-based Lagrangian and Hamiltonian equations have been proposed. The revised contradiction free local fractal calculus-based Lagrangian and Hamiltonian equations have been presented. A comparison of local and nonlocal fractal calculus in terms of Lagrangian and Hamiltonian formalisms have been made where a drawback of the nonlocal one has been pointed out.

The theoretical method of converting the magnetic circuit into an electric circuit is mature, but the way to determine the inductances in the electric circuit is not reliable, especially for the core working in saturation status, and it is impossible to determine the inductances by the transformer terminal measurements, as the measurement information is not enough to determine a number of inductances. This paper aims to propose an approach of calculating the reluctances.

In this paper, an approach of calculating the reluctances is proposed based on the numerical simulation of magnetic field in transformer with different values of current excitation. The reluctance of a core segment or air region as a branch of magnetic circuit is obtained by the magnetic energy and magnetic flux. By this way, all the reluctances as function of flux can be determined, and then the inductances can be determined. The reluctances and equivalent electric circuit of three-phase integrative transformer is determined, and its validation is proved in the paper.

The single phase example shows that the proposed method has a good performances on analysis of the inrush current in deep saturation. The peak value of the inrush current derived from the proposed approach matches well with the results obtained by coupled circuit-FEM analysis, and the difference is about 4.8 per cent. For studies on dual models of single phase transformers, the leakage inductances have important effects on the peak value of the inrush current. The reluctances of three-phase transformer are calculated, and the equivalent circuit simulation results are slightly smaller than the coupled circuit-FEM simulation results.

Approach of calculating the reluctances based on the numerical simulation of magnetic field in transformer is proposed. The magnetic core and air space are divided into several segments, and the reluctance for each segment is calculated based on the energy in the region and the flux of the cross-sectional area. By applying various excitation currents, all the reluctances as function of flux can be determined, and then all the non-linear inductances including the non-linear leakage inductances are obtained. The proposed approach is reliable to determine a number of inductances in the dual electric circuit, especially for deep saturation status.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.