Search results

1 – 10 of over 1000
Article
Publication date: 1 December 1997

K. Boustedt and E.J. Vardaman

Theelectronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip isgoing to become the major alternative for future products. The user wants more…

285

Abstract

The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.

Details

Microelectronics International, vol. 14 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Content available
Article
Publication date: 1 June 2004

85

Abstract

Details

Circuit World, vol. 30 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Content available
Article
Publication date: 1 April 2004

46

Abstract

Details

Soldering & Surface Mount Technology, vol. 16 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

Content available
Article
Publication date: 1 August 2003

94

Abstract

Details

Soldering & Surface Mount Technology, vol. 15 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Content available
Article
Publication date: 1 April 2004

Bob Willis

56

Abstract

Details

Microelectronics International, vol. 21 no. 1
Type: Research Article
ISSN: 1356-5362

Content available
Article
Publication date: 1 March 2005

304

Abstract

Details

Circuit World, vol. 31 no. 1
Type: Research Article
ISSN: 0305-6120

Content available
Article
Publication date: 1 December 2004

90

Abstract

Details

Soldering & Surface Mount Technology, vol. 16 no. 3
Type: Research Article
ISSN: 0954-0911

Article
Publication date: 4 September 2017

Fang Liu, Jiacheng Zhou and Nu Yan

The purpose of this paper is to study the drop reliability of ball-grid array (BGA) solder joints affected by thermal cycling.

Abstract

Purpose

The purpose of this paper is to study the drop reliability of ball-grid array (BGA) solder joints affected by thermal cycling.

Design/methodology/approach

The drop test was made with the two kinds of chip samples with the thermal cycling or not. Then, the dyeing process was taken by these samples. Finally, through observing the metallographic analysis results, the conclusions could be found.

Findings

It is observed that the solder joint cracks which were only subjected to drop loads without thermal cycling appeared near the BGA package pads. The solder joint cracks which were subjected to drop loads with thermal cycling appear near the printed circuit board pads.

Originality/value

This paper obtains the solder joint cracks picture with drop test under the thermal cycling.

Details

Soldering & Surface Mount Technology, vol. 29 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 December 1997

J.H. Lau

Theexplosive growth of high‐density packaging has created a tremendous impact on theelectronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip ScalePackaging

665

Abstract

The explosive growth of high‐density packaging has created a tremendous impact on the electronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip Scale Packaging (CSP), Direct Chip Attach (DCA), and flip‐chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. In this paper, they will be briefly discussed.

Details

Circuit World, vol. 23 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 January 1990

J.H. Lau, S.J. Erasmus and D.W. Rice

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is…

209

Abstract

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

Details

Circuit World, vol. 16 no. 2
Type: Research Article
ISSN: 0305-6120

1 – 10 of over 1000