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The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.

This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization.

The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number.

Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency.

The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments.

The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

Known good die, flip chip and chip scale packages are technologies that offer various advantages to the board manufacturer. A discussion of the different types of package options, their methods of assembly, test and performance comparisons can help to resolve the general direction a manufacturer might pursue for next generation systems. This paper attempts to give a perspective as well as highlighting the areas of concern with the different options.

Customer demand is driving the evolution of electronic equipment towards smaller devices with increased performance and more features. At the same time, product price should remain at a sufficiently low level with assembly process yields and throughput high. These somewhat contradictory requirements are difficult to fulfil with conventional SMD technology. Therefore, much attention is paid to packages offering small‐size and high I/O counts as well as excellent electrical properties, such as chip scale packages (CSP) and flip‐chip. CSP offers an IC in a package, which provides robustness for handling and, in some cases, decreases thermally induced stresses, and, most importantly, is SMT compatible. On the other hand, flip‐chip has the ultimate electrical performance and the smallest “package” size, with the capability of very high I/O counts. In this paper, the impacts of both CSP and flip‐chip technologies on product development and manufacturing processes is addressed.

A new solder‐bumped flip chip land grid array (LGA) chip scale package (CSP) called NuCSP is presented in this paper. NuCSP is a minimized body size package with a rigid substrate (interposer). The design concept is to utilize the interposer to redistribute the very fine pitch peripheral pads on the solder‐bumped chip to much larger pitch area‐array pads on the printed circuit board (PCB). Using conventional PCB substrate manufacturing processes, NuCSP offers a very low‐cost package suitable for memory chips and low pin‐count application‐specific ICs (ASICs). Also, NuCSP is surface mount technology (SMT) compatible and can be joined to the PCB with a 6‐mil (0.15mm) thick 63wt %Sn‐37% Pb solder paste.

The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided.

The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed.

The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip.

It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work.

It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data.

This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five‐point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

Presents a new wire bondable land grid array (LGA) chip scale package called NuCSP. NuCSP is a minimized body size wire bondable package with rigid substrate interposer. The design concept is to utilize the plating bars on the edges of the package substrate as the wire bond fingers. Bond fingers are redistributed inward to an array of plated through hole vias underneath the chip, then are connected to copper pads on the bottom of the package. NuCSP package size is about equal to die size + 3 mm. Using conventional PCB substrate manufacturing with 4/4 mils routing width/space and wire bonding process, NuCSP offers a very low cost package suitable for memory chips and low pin count application specific IC (ASIC) applications. The other advantages are that the use of wirebonding allow NuCSP be applicable for die size, pad count and pitch variations. Because it is wire bondable, NuCSP may be as generic as plastic quad flat pack (PQFP), yet providing smaller body size, lower cost and smaller package electrical parasitic parameters.

The explosive growth of high‐density packaging has created a tremendous impact on the electronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip Scale Packaging (CSP), Direct Chip Attach (DCA), and flip‐chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. In this paper, they will be briefly discussed.