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The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided.

The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed.

The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip.

It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work.

It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data.

This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.

Customer demand is driving the evolution of electronic equipment towards smaller devices with increased performance and more features. At the same time, product price should remain at a sufficiently low level with assembly process yields and throughput high. These somewhat contradictory requirements are difficult to fulfil with conventional SMD technology. Therefore, much attention is paid to packages offering small‐size and high I/O counts as well as excellent electrical properties, such as chip scale packages (CSP) and flip‐chip. CSP offers an IC in a package, which provides robustness for handling and, in some cases, decreases thermally induced stresses, and, most importantly, is SMT compatible. On the other hand, flip‐chip has the ultimate electrical performance and the smallest “package” size, with the capability of very high I/O counts. In this paper, the impacts of both CSP and flip‐chip technologies on product development and manufacturing processes is addressed.

The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. They will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the future. The requirements for further CSP assembly studies will also be addressed in this paper.

The explosive growth of high‐density packaging has created a tremendous impact on the electronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip Scale Packaging (CSP), Direct Chip Attach (DCA), and flip‐chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. In this paper, they will be briefly discussed.

A new solder‐bumped flip chip land grid array (LGA) chip scale package (CSP) called NuCSP is presented in this paper. NuCSP is a minimized body size package with a rigid substrate (interposer). The design concept is to utilize the interposer to redistribute the very fine pitch peripheral pads on the solder‐bumped chip to much larger pitch area‐array pads on the printed circuit board (PCB). Using conventional PCB substrate manufacturing processes, NuCSP offers a very low‐cost package suitable for memory chips and low pin‐count application‐specific ICs (ASICs). Also, NuCSP is surface mount technology (SMT) compatible and can be joined to the PCB with a 6‐mil (0.15mm) thick 63wt %Sn‐37% Pb solder paste.

The purpose of this paper is to describe the board level reliability test results of four IC packages with lead‐free balls/platings, soldered with lead‐free solder paste, during thermal cycling. The board level reliability test results of tin‐lead balled/plated packages soldered with lead‐free solder paste have also been included for comparison.

Four different packages, i.e. ball grid array (BGA), chip scale package (CSP), quad flat package (QFP) and thin small outline package (TSOP), were assembled on a test printed circuit board (PCB) as the test vehicle. Lead‐free and tin‐lead BGA/CSP packages were equipped with Sn‐3.0Ag‐0.5Cu and Sn‐37Pb solder balls, respectively. The lead‐frames of lead‐free QFP/TSOP leaded‐packages were plated with Sn‐58Bi and those of tin‐lead QFP/TSOP leaded‐packages, Sn‐37Pb. The lead‐free solder paste used in this study was Sn‐3.0Ag‐0.5Cu. Two kinds of surface finishes, immersion gold over electroless nickel (Au/Ni) and organic solderability preservative, were used on the PCBs. The test PCBs were thermal cycled 5,000 times within the temperature range of −40 to 125°C and electrically monitored during the thermal cycling.

It was found that the tin‐lead balled/plated BGAs, CSPs, QFPs and TSOPs soldered with lead‐free solder paste showed serious board level reliability risks as their abilities to withstand thermal cycling stresses are much weaker than those of entirely lead‐free assemblies. Neither package nor surface finish was found to have any effects on the board level reliability of test vehicles with lead‐free balled/plated BGAs, CSPs, QFPs and TSOPs. Metallographic examinations were conducted to investigate the effect of thermal cycling on the failure modes of solder joints.

The paper is of value by contributing to research in the use of lead‐free solder paste with lead‐containing packages in the industry. Currently, there is a deficiency of knowledge in this area.

Presents a new wire bondable land grid array (LGA) chip scale package called NuCSP. NuCSP is a minimized body size wire bondable package with rigid substrate interposer. The design concept is to utilize the plating bars on the edges of the package substrate as the wire bond fingers. Bond fingers are redistributed inward to an array of plated through hole vias underneath the chip, then are connected to copper pads on the bottom of the package. NuCSP package size is about equal to die size + 3 mm. Using conventional PCB substrate manufacturing with 4/4 mils routing width/space and wire bonding process, NuCSP offers a very low cost package suitable for memory chips and low pin count application specific IC (ASIC) applications. The other advantages are that the use of wirebonding allow NuCSP be applicable for die size, pad count and pitch variations. Because it is wire bondable, NuCSP may be as generic as plastic quad flat pack (PQFP), yet providing smaller body size, lower cost and smaller package electrical parasitic parameters.

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.

As part of a programme of characterisation of interconnection technologies for computer server products the present investigation was conducted to determine the attachment integrity and long‐term reliability of resistor network ceramic Chip Scale Package (CSP) solder joints. Accelerated thermal cycling with electrical continuity monitoring of the solder joints was used to determine reliability. The thermal cycling was combined with metallographic examination of appropriate solder joints to evaluate the failure modes and to corroborate the failure thresholds. The measured reliability for the CSP solder joints was 1,027 thermal cycles. This implied an estimated minimum lifetime of 7.8 years for the product in a worst‐case field use. The reliability was virtually unaffected by the solder joint pad size and geometry on the board. All fatigue failed solder joints exhibited similar failure modes.