Search results

As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost miniaturisation is flip‐chip assembly on FR4 boards. In this paper, two types of flip‐chip assembly process will be discussed: a process where flip‐chips with eutectic solder‐bumps are assembled by using a tacky flux, and a process where flip‐chips are assembled by using solder paste. Both processes have been verified on production boards, using production equipment. Demonstrated ppm defect levels are between 35 and 400 ppm (confidence level 95 per cent) at the solder joint level. Component yields for flip‐chips are between 99.2 and 100 per cent. The reliability of the assemblies fulfils consumer communication equipment requirements.

A flip chip on board technology fully compatible with current PCB facilities is reported. It used reflow soldering for chip attachment. It required electroless nickel/immersion gold finishing on the board pads as well as on the chip pads. A no‐clean solder paste was printed on the boards before chip placement. Thus, there was no requirement for solder deposition on the chip side. Assembly tests with various chip formats proved the feasibility of this technology. X‐ray inspection and cross‐sectioning revealed the good shape and alignment of the reflowed solder joints. The reliability of underfilled assemblies was studied by ‐40 to 125°C thermal cycling. This approach is especially suitable for prototype or low volume productions as it eliminates the solder bumping process on the chip side, which is usually performed on the wafer level.

The mechanical and thermal responses of encapsulated flip chip solder bumps on a surface laminar circuit (SLC) board have been determined in this study. The mechanical responses of the solder bumps and encapsulant have been obtained by shear, tension and torsion tests. The thermal stress and strain in the solder bumps and encapsulant have been determined by a non‐linear finite element method and the thermal fatigue life of the corner solder bump is then estimated based on the calculated plastic strains, Coffin‐Manson law and isothermal fatigue data of solders. Also, an assembly process of the test boards is presented.

Known good die, flip chip and chip scale packages are technologies that offer various advantages to the board manufacturer. A discussion of the different types of package options, their methods of assembly, test and performance comparisons can help to resolve the general direction a manufacturer might pursue for next generation systems. This paper attempts to give a perspective as well as highlighting the areas of concern with the different options.

Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.

As requirements for system performance and density increase, more attention is being given to chip‐on‐board (COB) packaging techniques. COB is ‘surface mount packaging taken to the extreme’ as it involves the direct mounting of bare semiconductor die to printed circuit board substrates. In this paper, the ‘thermal resistance’ of a single COB package is proposed. An analytical model for this resistance is developed for a multilayer board configuration using a combination of Fourier transform and adjoint‐solution techniques. Parameters in the model include the chip and board geometric parameters, individual layer unit conductances, and top and bottom surface film coefficients. A series of curves are developed from the model. These curves may be used in the initial design process to determine, for example, required film coefficients and the efficacy of adding thermal planes to the board. The model is also used to test the adequacy of the ‘effective series conductivity’ of a multilayer board.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

Flip chip test boards with and without plasma enhanced chemical vapor deposition silicon nitride moisture barrier coatings were exposed to high humidity and temperature cycling conditions. The effect of the stress developed in these environments was investigated and evaluated. The influence of the barrier layers on the extent of underfill delamination and degradation in flip chip assemblies was inspected by C‐mode Scanning Acoustic Microscopy. The moisture barrier layers studied show their potential to enhance the reliability of flip chip assemblies in humid environments.

The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided.

The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed.

The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip.

It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work.

It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data.

This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.

This paper discusses chip removal and replacement processes of flip chip assemblies (FCAs) on printed wiring boards (PWBs). The original chip connection is achieved via mass reflow as in a surface mount assembly process. The FCA interconnection is one involving a surrogate solder bump on a chip and a lower melt solder on the PWB pads that fuses with the bump during reflow. The chip removal process thus entails melting the lower melt solder locally using hot gas. The following considerations will be discussed in the paper: chip size, chip removal methodology, local vs mass reflow for replacement attachment, solder height, the impact of multiple reflows on the solder joint integrity of assemblies. The use of the flip chip rework machine to remove ball grid arrays (BGAs) and quad flatpacks (QFPs) will be briefly addressed.