Search results

The purpose of this paper is to deal with material and technological aspects of SiC diodes assembly in ceramic packages. The usefulness of combinations of different materials and assembly techniques for the creation of inner connection system in the ceramic package, as well as the formation of outer connections able to work at temperatures up to 350°C, were evaluated.

The ceramic package consists of direct bonded copper (DBC) substrate with Cu pads electroplated by Ni or Ni/Au layers on which a SiC diode was assembled by sintering process using Ag microparticles. For the connections inside the ceramic package, the authors used Al/Ni and Au-Au material system based on aluminium or gold wire bonding. The authors sealed the ceramic package with glass encapsulation and achieved a full encapsulation. Outer connections were manufactured using Cu ribbon plated with Ag layer and sintered to DBC by Ag micro particle. The authors investigated the long-term stability of electrical parameters of SiC diodes assembled in ceramic package at temperature 350°C.

The authors have shown that Schottky and PiN SiC diodes assembled with different technologies and materials in ceramic package keep their I-V characteristics unchanged during ageing at 350°C for 400 h.

The SiC diodes assembled into ceramic package with Al/Ni or Au-Au inner electrical connection systems and outer connections system based on Ag microparticles sintering process of Cu/Ag ribbon to DBC substrate can work reliably in temperature range up to 350°C.

Vertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm² VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.

Following the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.

As a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.

The purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm² chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.

The purpose of this paper is to investigate the thermal behaviors of high power LED packages to enhance the thermal performances of low temperature co‐fired ceramic chip on board (LTCC‐COB) package. Thermal analysis demonstrated an improved LTCC‐COB package design that is comparable to a metal lead frame package with low thermal resistance.

The LED device developed in this study is a LTCC package mounted directly on the metal PCB. A numerical simulation was performed to investigate the thermal characteristics of the LED module using the finite volume method, which is embedded in commercial software (Fluent V.6.3). Thermal resistance and temperature measurement validate the simulated results.

The effect of the thickness of the die attach material on the thermal resistance was dominant due to low thermal conductivity, and the junction temperature decreased significantly with slight increases in thermal conductivity, especially when the value was less than 5 W/mK. The results reveal that the thermal resistance of MCPCB is about 49 per cent‐58 per cent of the junction to board thermal resistance. The thermal model results showed good agreement with experimental results.

The developed model overcomes the large thermal resistance of a conventional LTCC package for high power LED module. The extensive results have demonstrated an improved thermal design, optimal dimensions of each component and boundary conditions for high power LTCC‐COB type package.

A review is given of the reliability of the ceramic chip carrier when solder‐attached to alumina thick film substrates. It is shown that no degradation occurs during humidity cycling or humidity steady state tests. Some diminution of the solder joint strength takes place during prolonged high temperature storage and temperature cycling but the effect is much more marked during power cycling. The effect of flux residues on thick film hybrids after solder reflow of surface mount components is assessed. No significant deterioration of any component, printed or discrete, that is attributable to flux is observed, given adequate cleaning techniques. The reliability of the ceramic leadless chip carrier is compared with both leaded ceramic and metal and plastic surface‐mountable components. The compliant leads of packages offer some advantages over the leadless chip carrier where thermal excursions are important but the leads themselves are easily damaged. Plastic packaging for surface‐mountable components continues to improve and become increasingly popular but potential reliability hazards associated with a thermal management performance inferior to that of ceramic and metal versions, moisture ingress and corrosion are seen to remain problem areas.

Because they offer many properties favourable for IC package construction, ceramics have been in widespread use as an electronic package material since the early 1960s. In recent years, with trends towards higher speed semiconductors generating up to 30‐40 watts power, packaging materials must possess excellent thermal, electrical and mechanical properties. Aluminium nitride, with a thermal conductivity of 170 W/m.K., high fracture strength and a thermal coefficient of expansion match with silicon, has been used to manufacture multilayer LGA (land grid array) packages for high performance applications. A 725 AIN LGA has been manufactured and its performance characteristics have been compared with those of an alumina (with copper/tungsten slug) packaging alternative. Because of the high thermal conductivity of aluminium nitride, all designs can be made in a cavity‐up configuration, resulting in significant package body size reduction. The area under the cavity can be used for increasing I/O number and a ground plane can be inserted under the cavity, reducing simultaneous switching noise. Aluminium nitride is particularly beneficial for flip‐chip interconnection. Its close TCE match to silicon eliminates the stress reduction requirement for die underfill.

The Benelux chapter has made a habit of organising meetings with a scientific and commercial accent more or less alternately. This approach has proven to be successful in the past three years. The 1986 Autumn meeting will be another display meeting. A number of papers will be presented by suppliers of materials and equipment for the hybrid and surface mounting industry. In a 300 m2 exhibition room about 25 companies will display their products. The programme of the day leaves ample opportunity for meeting colleagues and suppliers. The meeting will be held in the ‘Jaarbeurs Vergadercentrum’ in Utrecht on 16 October from 9.30–17.00. The annual ISHM‐Benelux general membership meeting will precede the lectures.

A reliable packaging process for flip chip on ceramic substrate using gold bumps and adhesive was successfully developed. The bonding parameters and flip chip assemblies using four adhesive materials were investigated by means of design of experiments and yield runs. The packaging yield was 100 per cent. All the packages assembled during the yield runs passed various reliability tests. The packages attained 100 per cent reliability required for an industrial application.

The International Electronic Components Show in Paris in November, 1983, provided the occasion for a very successful meeting of ISHM‐France which attracted 170 attendees. The following presentations were given:

The use of Taguchi experimental design techniques to examine the effects of package type, solder paste type and solder reflow technique on the quality of fine pitch surface mount IC package solder joints is described. In particular, the effect of the use of ceramic or plastic packages, copper or Alloy 42 leadframes, silver loaded or non‐silver loaded solder paste and infra‐red, laser or hot‐bar reflow on solder joint metallurgical structure, electrical resistance and mechanical strength is evaluated. In addition to these solder joint parameters, an associated visual inspection was used to find the best process parameters to minimise solder balling, bridging etc. and a correlation between paste contacts at placement and solder bridges after reflow was also conducted. The experiment used an L9 array to find the optimum parameters from three factors, each at three levels. An extension to the basic Taguchi array was included in the form of an outer (noise) factor to include the effect of climatic stress on the solder joints under investigation. Response tables separate out the contribution of each factor level to the mechanical strength and electrical resistance of the assemblies. By comparing the response tables before and after climatic testing it is possible to estimate the effect of each factor level on the long‐term quality of the solder joints. It is shown how Taguchi experimental design techniques can be used to minimise the number of experiments required to predict optimum solder assembly process parameters. The accuracy of the prediction is shown by the results of a confirmation run which yielded mechanical strengths very close to those predicted, both before and after highly accelerated stress testing of the solder assemblies.

A high‐density module for image processing was developed by chip‐on‐wafer technology. A silicon wafer was used as the substrate and the LSI chips were flip‐chip bonded to the silicon wafer by bumps in chip‐on‐wafer technology. A primary benefit of using a silicon wafer is the little induced thermal stress which affects the bumps. The module contained a digital signal processor, SRAMs and other peripheral LSls. A total of sixteen chips were bonded on the wafer. The LSIs were connected to each other by copper/polyimide multilayer interconnections consisting of eight copper conductive layers and polyimide dielectric layers. The characteristic impedance for the signal lines was controlled to 50 ohms. The LSIs were connected to the wafer electrically and mechanically by solder bumps, which were formed on the LSI bonding pads. A 188 pin AIN ceramic package was used for the module in order to obtain high heat radiation and high reliability. The occupied area for the module was reduced to 20%, compared with the size for conventionally assembled DIPs on a PC board.