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This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.

This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.

It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.

Compact Analytical models for undoped symmetric double gate MOSFETs.

Following extensive studies that demonstrated that some types of plastic encapsulation can be used in high reliability environments, the EPIC chip carrier was conceived and developed as a cost‐effective micropackage for ICs. The EPIC chip carrier is manufactured by adaptations of PCB techniques with metallisation suitable for auto‐wire bonding. It is a low‐cost alternative to the ceramic chip carrier, but with a much better electrical performance, derived from lower parasitics of the materials employed. Reliability studies have confirmed the suitability of the EPIC for 20 year life operations to which an added benefit is the avoidance of TCE mismatch problems sometimes obtained with ceramic chip carriers on PCBs.

Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs.

The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix.

Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles.

The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results.

The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.

The purpose of this paper is to evaluate the conditions in which a saturation of the common mode (CM) choke might appear to be essential for proper design of the CM voltage filters. This paper presents a method for the determination of a CM choke flux density produced by multilevel inverters with carrier‐based modulations.

The proposed combination of secant and tangent methods allows efficient and high‐resolution determination of the CM voltage waveforms produced at the output of the multilevel inverters with commonly used carrier‐based modulations.

The presented results show that the application of a five‐level inverter with specific modulation causes a decrease of the maximum flux density, down to 15 per cent of the maximum level of the flux density reached in a two‐level inverter. The proposed, dedicated approximation method provides an accuracy of the root estimation better by about three orders for a comparable number of the function calls in comparison with Brent's method.

The presented theoretical evaluations make possible the determination of the maximum expected value of the flux density produced by multilevel inverters with various types of carrier‐based modulations, which allows a reduction in dimensions, weight and cost of CM chokes applied in CM voltage compensators.

In the paper, the new formulas that describe the placement of triangular carrier functions for commonly used multilevel inverters have been presented. In order to avoid accumulation of the estimation error, during determination of the CM voltage time integral, a dedicated, efficient method of roots approximation has been developed.

This paper aims to develop a method for a unified model of pulse width modulation (PWM) voltage source inverters (VSI). This generic method, based on a common and easy-to-use carrier-based modulation, allows to generate the exhaustive solution set for a given PWM-VSI.

The use of the generalized inverse theory is developed to express the PWM solution set for the duty cycle. Indeed, the infinite number of PWM solutions is demonstrated. To explore this solution set, the unified model described exhibits degrees of freedom. The admissible margins to set the degree of freedom are highlighted. Some experimental results are presented.

It is demonstrated how the degree of freedom can be directly connected with efficiency indicators such as common mode voltage, inverter linearity and switching losses. The expression of the PWM solution set boundaries is clearly expressed.

Further studies should explore how the degree of freedom can be connected with parameters associated with the current (and not the voltage as described in this paper).

The paper includes implications for the development of a more generic approach for PWM multilevel VSI.

This paper fulfils a mathematical frame to ease the expression of PWM scheme.

This paper aims to propose a bidirectional hidden converter (BHC)-based three-phase DC–AC conversion for energy storage application. BHC is the new concept to vary an energy storage device voltage into wide range. Hidden converter power loss and power rating are reduced by using zero-sequence injection-based carrier-based pulse-width modulation (CBPWM) strategy.

By using this control strategy, a BHC processes only little amount of power during double-stage conversion, mostly during direct or single-stage conversion of the three-phase three-port converter (TPTPC) only processing the maximum power.

TPTPC consists of two sets of positive group switches for inversion process, one set of switches is regular inverter switches called vertical positive group switches, and the second set is anti-series switches, which are horizontally connected for direct or single-stage conversion.

Characteristics, principles and implementations of proposed DC–AC 3Ø conversion system and its PWM strategy are analyzed. Through experimental outputs, the effectiveness and viability of the proposed solutions are validated.

This paper aims to propose a novel model predictive control (MPC) with time varying weights to develop a lateral control law in an automatic carrier landing system (ACLS), which minimizes landing risk and improves flight quality.

First, a nonlinear mathematic model of an F/A-18 aircraft during lateral landing is established. Then the landing model is linearized in the form of state deviations on the equilibrium points. Second, landing risk windows are proposed and a high-dimensional landing risk model is addressed through a back propagation (BP) neural network. The trained samples are acquired based on a pilot behavior model. Third, time varying weights created from the lateral landing risk are introduced into the performance function of MPC. Optimal solution is solved quicker and some state deviations are focused on and eliminated. Fourth, the algebraic inequalities are substituted by the linear matrix inequalities (LMIs), which are easily calculated by the computers.

On a semi-physical platform, the proposed method compares with a traditional MPC algorithm and a modified MPC with an additional term. The test results indicate that the proposed algorithm brings about an excellent landing performance as well as an ability of eliminating landing risk.

The landing phase of a carrier-based aircraft is one of the most dangerous and complicated stages, and the algorithm proposed by this paper plays a vital role in the lateral landing.

This paper establishes a lateral landing risk model, which considers not only the current landing state but also the future touchdown point. This lateral landing risk is integrated into the time varying weights of the MPC algorithm so that the state deviations and landing risk can be both reduced in the rolling optimization.

This paper aims to propose Hidden Converter (H-Converter) combined with dual port 3Ø inverter for energy storage application to produce wide range of voltage. Some of the application required wide range of voltages, but problem from E-chopper is either boost or buck mode of operations, both modes are not possible. To overcome this drawback, H-Converter is combined with dual port 3Ø inverter controlled by carrier-based pulse width modulation (CB-PWM) technique is added with zero sequence injection.

Hidden converter is a bidirectional DC-DC chopper used to convert fixed DC to variable DC and vice versa in both buck and boost modes of operations. Dual port inverter is combined with hidden DC-DC converter can produce wide range of voltages.

The bidirectional DC-AC converter requires less power for processing and consumes less power losses by using modest carrier built- pulse width modulation scheme through proposed zero structure addition.

By using this proposed strategy H-Converter can produce wide range of voltage in both the sides and mostly power is processed in the 3Ø inverter with a one stage conversion with less power loss. As a result, with one stage power conversion has more efficiency because of less power loss. This proposed converter has designed by analysis, and the real time result is tested in an experiment.

An enterprise’s telecommunications network is central to successful development and implementation of corporate strategy in the single European market. Considers how and by whom this strategic resource should be managed. Highlights the corporate networking options: public networking, insourcing, outsourcing, market trends and the effects future regulation may have on the market.