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This paper aims to develop a capacitor position in radial distribution networks with a specific end goal to enhance the voltage profile, diminish the genuine power misfortune and accomplish temperate sparing. The issue of the capacitor situation in electric appropriation systems incorporates augmenting vitality and peak power loss by technique for capacitor establishments.

This paper proposes a novel strategy using rough thinking to pick reasonable applicant hubs in a dissemination structure for capacitor situation. Voltages and power loss reduction indices of distribution networks hubs are shown by fuzzy enrollment capacities.

A fuzzy expert system containing a course of action of heuristic rules is then used to ascertain the capacitor position appropriateness of each hub in the circulation structure. The sizing of capacitor is solved by using hybrid artificial bee colony–cuckoo search optimization.

Finally, a short-term load forecasting based on artificial neural network is evaluated for predicting the size of the capacitor for future loads. The proposed capacitor allocation is implemented on 69-node radial distribution network as well as 34-node radial distribution network and the results are evaluated.

Simulation results show that the proposed method has reduced the overall losses of the system compared with existing approaches.

The purpose of this paper is to present work on the incorporation of capacitors into printed circuit boards (PCB) as a method to measure moisture content and follow moisture diffusion under ground planes.

PCBs were manufactured of FR‐4 incorporating different arrangements and sizes of capacitors formed between the tracks on adjacent layers of the PCB. The boards were placed in an 85°C and 85 per cent relative humidity (RH) environment to absorb moisture before baking at temperatures of 80, 110 or 125°C with the capacitance periodically measured. The effect of ground planes with different densities of plated and non‐plated through holes (PTH) has been studied by placing capacitors between ground planes.

Parallel plate capacitors embedded within a PCB showed a 10 per cent capacitance increase going from a dry state to being saturated with moisture in an 85°C and 85 per cent RH environment. The slow ingression of moisture under the capacitance planes meant that the measured capacitance change did not reflect the moisture content of the remainder of the board well. Capacitor plates with slots for the moisture to penetrate were also investigated, with the increase in capacitance found to show good correlation with the increase in board mass. In investigating moisture under ground planes, either by decreasing the hole density or by plating the holes, the time for moisture to diffuse out of the board was found to increase due to the lower exposed area on the PCB.

The paper illustrates a method that can be applied to PCB manufacturing to assess the moisture content of a board prior to reflow.

The purpose of this paper is to share valuable information about low‐cost microwave circuit research with academic and industrial communities that work, or want to work, in this field.

Screen‐printing technology has been chosen as the fabrication method because of simplicity and low costs. Different materials and printing parameters were tested in four generations of microstrip lines. After obtaining a satisfactory fabrication method, passive microwave components were printed, assembled, characterized and modeled.

Results demonstrated that the proposed low‐cost method allows fabricating low loss microstrip lines (15.63×10⁻³ dB/mm at 10 GHz), filters, inductors, and capacitors that work well up to 12 GHz.

Model accuracy of inductors and capacitors can be improved. The use of more precise calibration and de‐embedding techniques is necessary. More components can be fabricated and modeled to increase the flexibility and applicability of the proposed fabrication method.

The presented information can help limited budget companies and small educational institutions in electronics to fabricate microwave circuits at low costs. This is an excellent approach for students who want to learn how to make microwave frequency measurements and circuits without the need of expensive fabrication equipment and clean rooms.

The step‐by‐step fabrication method described in this paper allows fabricating different microwave components at low costs. The presentation of electrical models for each component completes the design‐fabrication cycle. As this information is gathered in a single source, it makes easier the incursion of new actors in the microwave field.

Non‐corrosive rosin fluxes have historically been used for telephone communications assemblies because they provide a measure of reliability even if the flux is not totally removed from the assembly. While cleaning is not always necessary from a reliability standpoint, testing issues, product appearance, operating performance and customer requirements must also be considered when making the decision whether or not to clean. As the electronics industry packages more and more functionality on less and less real estate, soldering yields need to increase in order for the assembly process to remain profitable. This requires not only attention to the product's design for manufacturing but it may also require aggressive fluxes to be used in the assembly process. When aggressive fluxes are employed, the necessity for cleaning is greatly increased. The particular combination of flux and cleaning option depends on product design, process capabilities, end point requirements, and environmental considerations. Pending restrictions on the production and use of chlorofluorocarbons (CFCs), and the potential for tighter controls on chlorinated solvents and aqueous detergent effluents, are certain to add to the cost of standard processes. For these reasons alternative cleaning processes have been explored. The evaluation and subsequent use of water soluble flux with ‘water only’ cleaning, terpene cleaning of rosin flux residues, low solids flux ‘no‐clean’ wave soldering and ‘no‐clean’ assembly using reflowed rosin based solder pastes within AT&T are reviewed. A user's assessment of aqueous and semi‐aqueous cleaning is presented which indicates that there are acceptable alternatives to CFCs.

In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.

Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.

This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.

Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG).

The tunnelling and electron injection methods were applied to program FG devices of different lengths (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology.

Current leakages are increasing with device scaling and reducing the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered.

Although the results have raised further research questions, as revealed by certain reliability issues, they have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

The vacuum vapour phase soldering method was investigated by numerical simulations. The purpose of this study was to examine the temperature changes of the solder joints during the vapour suctioning process. A low pressure is used to enhance the outgassing of the trapped gas within the solder joints, which otherwise could form voids. However, the system loses heat near the suction pipe during the suctioning process, and it can result in preliminary solidification of the solder joints before the gas could escape.

A three-dimensional numerical flow model based on the Reynolds averaged Navier–Stokes equations with the standard k-e turbulence method was developed. The effect of the vapour suctioning on the convective heat transfer mechanism was described by the model. Temperature change of the solder joints was studied at the mostly used substrate and component combinations, as well as at different system settings.

In the function of the substrate thickness and the component size, the solder joints can lose large amount of heat during the void reduction process, which leads to preliminary solidification before the entrapped gas voids could be removed.

The results provide setting information of vacuum vapour phase technology for appropriate and optimal applications.

The relationship between low pressure generation and convective heat transfer mechanism during vacuum vapour phase soldering has not been studied yet. The possible negative effects of the vapour suctioning process on the solder joint temperature are unknown.

This paper aims to optimally plan distributed generation (DG) and capacitor in distribution network by optimizing multiple conflicting operational objectives simultaneously so as to achieve enhanced operation of distribution system. The multi-objective optimization problem comprises three important objective functions such as minimization of total active power loss (P^loss_total), reduction of voltage deviation and balancing of current through feeder sections.

In this study, a hybrid configuration of weight improved particle swarm optimization (WIPSO) and gravitational search algorithm (GSA) called hybrid WIPSO-GSA algorithm is proposed in multi-objective problem domain. To solve multi-objective optimization problem, the proposed hybrid WIPSO-GSA algorithm is integrated with two components. The first component is fixed-sized archive that is responsible for storing a set of non-dominated pareto optimal solutions and the second component is a leader selection strategy that helps to update and identify the best compromised solution from the archive.

The proposed methodology is tested on standard 33-bus and Indian 85-bus distribution systems. The results attained using proposed multi-objective hybrid WIPSO-GSA algorithm provides potential technical and economic benefits and its best compromised solution outperforms other commonly used multi-objective techniques, thereby making it highly suitable for solving multi-objective problems.

A novel multi-objective hybrid WIPSO-GSA algorithm is proposed for optimal DG and capacitor planning in radial distribution network. The results demonstrate the usefulness of the proposed technique in improved distribution system planning and operation and also in achieving better optimized results than other existing multi-objective optimization techniques.

The purpose of this study is to discuss the effect of hybrid cascode compensation with quality factor (Q-factor) control module for the three-stage amplifiers driving ultra-large load capacitors. Compared to the present frequency compensation solutions, it extends the amplifier bandwidth by establishing an extra AC feedback pathway besides the primary pathway through the Miller capacitor, increasing the loop gain at the gain–bandwidth product (GBW) frequency by pushing to the higher frequencies the nondominant poles.

A Q-factor control block is used to improve the damping factor of the compensation loop with no power or area overhead, thereby reducing the frequency peaking and the undesired oscillation in the time response for small load capacitors. The Q-factor control module is realized by a tiny-size on-chip capacitor, and provides an extra feedback loop to feed the damping current back to the input stage. A left-half-plane (LHP) zero is also introduced to further improve the stability.

A prototype of the proposed amplifier is simulated in 180-nm CMOS with a quiescent current of 24-µA from 1.80-V voltage supply. It achieves a 3.98-MHz gain–bandwidth product for 500-pF load capacitor, while the overall compensation capacitor is limited to 0.5-pF and the DC gain is extended beyond 100-dB.

The proposed amplifier is absolutely stable for the load capacitors ranging between 80-pF and 100-nF.

The frequency simulation and optimisation of electromagnetic compatibility (EMC) filter is often computation time consuming. The purpose of this paper is to propose an approach for easy and fast modelling and optimization of power electronics structures.

The paper proposes an approach for easy and fast modelling and optimization of power electronics structures. It focuses on the EMC filter design. To achieve this task time simulation, FFT and automatic frequency modelling are combined.

An automatic frequency modelling is proposed and also gives automatically the model gradients. Therefore, the model can be used to optimize the EMC filter, but also can help in choosing its topology. Several optimization algorithms are used and compared.

The power electronics load is supposed to be a set of predefined harmonic sources, obtained by time simulation + FFT before the optimisation process.

The frequency model allows for the rapid designing and comparing of several structures or modelling hypothesis with regard to the parasitic elements and circuit imperfections.

The frequency model is automatically generated, and sizing criteria on the component (e.g. inductors, capacitor) can be added in an analytical form, for example, to deal with volume or mass criteria.