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The purpose of this paper is to develop an efficient numerical algorithm for the self‐consistent solution of Schrodinger and Poisson equations in one‐dimensional systems. The goal is to compute the charge‐control and capacitance‐voltage characteristics of quantum wire transistors.

The paper presents a numerical formulation employing a non‐uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrödinger equation through the split‐operator method while a relaxation method in the FTCS scheme (“Forward Time Centered Space”) is used to solve the two‐dimensional Poisson equation.

The numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge‐control characteristics and the capacitance‐voltage relationship for a split‐gate quantum wire device.

The paper helps to fulfill the need for C‐V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two‐dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one‐dimensional quantization case, significantly diminishing running time.

The purpose of this paper is to investigate the dark properties as a function of reverse current induced defects. Dark characteristics of solar modules are very essential in the understanding the functioning of these devices.

Reverse currents were applied on the photovoltaic (PV) modules to create defects. At several time intervals, dark characteristics along with surface temperature were measured.

Current-voltage (I-V) and capacitance-voltage (C-V) characteristics furnished valuable data and threshold values for reverse currents. Maximum module surface temperatures were directly related to each of the induced reverse currents and to the amount of leakage current. Microstructural damages, in the form of hot spots and overheating, are linked to reverse current effects. Experimental evidence showed that different levels of reverse currents are a major degrading factor of the performance of solar cells and modules.

These results give a reliable method to predict most of the essential characteristics of a silicon solar cell or a module. Similar test could help predict the amount of degradation or even the failure of PV modules.

The purpose of this paper is modeling the effect of negative capacitance in the capacitance-voltage characteristic of the intergranular potential barrier of varistor structure.

The modeling of the capacitance-voltage characteristic of the intergranular barrier in metal oxide varistor ceramics is based on the development of the algorithm. It includes all the known mechanisms of electrotransfer in a wide range of voltages and currents, and also takes into account the voltage drop on the intergranular interlayer of intergranular potential barrier.

The models and algorithms for calculating the capacitance-voltage characteristics of a single intergranular potential barrier with the use of the most established understanding used at the interpretation of the nonlinear conductivity intergranular barrier are developed. The results of the capacitance-voltage characteristics modeling correspond to the existing understanding of the electrical properties on the ac current varistor ceramics are based on zinc oxide. The model allows to predict the behavior of varistors on the alternating current (voltage).

It is established that the recharge of the surface localized states occurs when a voltage is applied to the varistor structure, it can lead to a relaxation decrease in the width of the potential barrier overcome by tunneling electrons in the field emission from the conduction band of the one crystallite in the conduction band of the other crystallite and thus to the current backlog of applied voltage on the phase (i.e. the expression of the negative capacitance effect).

Al₂O₃ used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.

Al₂O₃ film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N₂ at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al₂O₃/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.

RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al₂O₃/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.

The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al₂O₃/SiC capacitors suitable for flash memory applications is investigated in this paper.

The purpose of this paper is to electrically examine the quality of thin thermally grown SiO₂ with thickness variation, on Si‐face of 4H‐SiC <0001> (having 50 μm epitaxial layer) by current‐voltage (I‐V) and capacitance‐voltage (C‐V) methods.

Metal‐oxide‐silicon carbide (MOSiC) structures with varying oxide thickness have been fabricated on device grade 4H‐SiC substrate. Ni has been used for gate metal on thermally oxidized Si‐face and a composite layer of Ti‐Au has been used for Ohmic contact on the highly doped C‐face of the substrate. Each structure was diced and bonded on a TO‐8 header with a suitable wire bonding for further testing using in‐house developed LabVIEW‐based computer aided measurement setup.

The leakage current of fabricated structures shows an asymmetric behavior with the polarity of gate bias ( + V or −V at the anode). A strong relation of oxide thickness and temperature on effective barrier height at SiO₂/4H‐SiC interface as well as on oxide charges have been established and reported in this paper.

The paper focuses on the development of 4H‐SiC based device technology in the fabrication of MOSiC‐based integrated structures.

The purpose of this paper is to report the effect of sputtering time on the electrical and physical properties of ZrO_x. ZrO_x (measured thickness is ranging from 20.5 to 51.3 nm) thin films as gate oxide materials are formed by metal deposition at different sputtering time and thermal oxidation techniques.

Zirconium is deposited on silicon substrate at three different sputtering time; 30‐, 60‐ and 120‐s continued with an oxidation process conducted at 500°C for 15 min to form ZrO_x thin films. High‐resolution X‐ray diffraction (HR‐XRD), Fourier transform infrared (FTIR) spectroscopy and electrical characterizations were used to examine the properties of the thin film.

A broad ZrO_x peak lies in between 26° and 31° from HR‐XRD is presumed as the effect of small thickness of ZrO_x and or the ZrO_x is still partially crystalline. FTIR spectroscopy results suggested that besides ZrO_x, SiO_x interfacial layer (IL) has also formed in all of the investigated samples. As the sputtering time increases, hysteresis between the forward and reverse bias of capacitance‐voltage curve has reduced. The lowest leakage current density and the highest oxide breakdown voltage have been demonstrated by 60‐s sputtered sample. These may be attributed to a lower effective oxide charge and interface trap density. The extracted dielectric constant (κ) of these oxides is ranging from 9.4 to 18, in which the κ value increases with the increase in sputtering time.

ZrO_x thin film which was fabricated by sputtering method at different sputtering time and thermal oxidation techniques showed distinctive electrical results. SiO_x IL formed in the samples.

The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.

The present experiments are intended to help characterize defects in very thin MOS oxide and at its Si/SiO₂ interface using a temperature‐dependent electrical characterization method, high low temperature capacitance voltage method and, especially, to investigate high temperature range. Oxide‐fixed traps are differentiated from slow‐state traps and from fast‐state traps by evaluating their electrical behaviour at different temperatures. The analysis points out the excess current after Fowler Nordheim electron injection based on hole generation, trapping, and hopping transport at high temperatures. The defect relaxation property versus temperature is investigated and defect relaxation activation energies are calculated. Creation mechanisms of interface states are especially identified by injection at different temperatures and these are compared with the other two kinds of defects. Fast‐state traps and all defect cross‐sections are calculated along and their creation activation energies are determined from Arrhenius plots.

The purpose of this study was to deposit Bi₄Ti₃O₁₂ films by electron gun evaporation technique starting from Bi_3.25La_0.75Ti₃O₁₂ as a target without annealing. The films have been deposited on Si(100), on thin film buffer layer of Pt and glass substrates. X-ray diffraction (XRD) was used to analyze structure of the films, which possesses a good structure with (0010) preferred orientation. Electronic behavior of the samples has been studied.

The dependence of both the structure and quality of the BLT thin films on different substrates is studied using XRD. The electrical characteristics were determined using capacitance–voltage (C–V) and current–voltage (I–V) measurements at the frequency of 1 MHz. Optical properties of the grown films deposited on glass substrates were characterized by optical transmittance measurements (UV-Vis).

The XRD analysis approved the crystallographer structure of the prepared Bi₄Ti₃O₁₂ films. The optical properties of deposited film (transmittance and the band gap value) are extracted by UV-Vis spectrum.

High crystalline quality Bi₄Ti₃O₁₂ films have been obtained using different substrates at room temperature by means of electron gun deposition. The electrical and ferroelectric properties of thin films were studied using I–V and C–V measurements. The band gap has been found to be about 3.62 eV for the studied film deposited on glass substrate. Electron beam evaporation technique is the most interesting methods, once considering many advantages; such as its stability, reproducibility, high deposition rate and the compositions of the films are controlled.