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Article
Publication date: 1 April 1998

Petri Savolainen

Customer demand is driving the evolution of electronic equipment towards smaller devices with increased performance and more features. At the same time, product price should…

269

Abstract

Customer demand is driving the evolution of electronic equipment towards smaller devices with increased performance and more features. At the same time, product price should remain at a sufficiently low level with assembly process yields and throughput high. These somewhat contradictory requirements are difficult to fulfil with conventional SMD technology. Therefore, much attention is paid to packages offering small‐size and high I/O counts as well as excellent electrical properties, such as chip scale packages (CSP) and flip‐chip. CSP offers an IC in a package, which provides robustness for handling and, in some cases, decreases thermally induced stresses, and, most importantly, is SMT compatible. On the other hand, flip‐chip has the ultimate electrical performance and the smallest “package” size, with the capability of very high I/O counts. In this paper, the impacts of both CSP and flip‐chip technologies on product development and manufacturing processes is addressed.

Details

Microelectronics International, vol. 15 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 December 2001

Subhotosh Khan and Dan J. Molligan

Personal electronic devices at the user interface, like cell phones, utilize BGA/CSP structure for miniaturization of circuits. These structures are subjected to severe thermal…

Abstract

Personal electronic devices at the user interface, like cell phones, utilize BGA/CSP structure for miniaturization of circuits. These structures are subjected to severe thermal loads due to environment of use. Starting with a microstructure of a failed board due to thermal cycles, the stresses/strains in this structure were analyzed from –408C to 1258C. In the finite element models (ABAQUS), we represented the structure as a composite of three‐dimensional (3‐D) elastic materials. The model showed stress/strain/energy concentrations at the actual failure points. The model also provided a route to improved durability by reducing these failure potentials, through change in the substrate of the printed circuit board (PCB). We observed significant reduction in failure potential when resin coated copper was replaced by THERMOUNT1 in PCB. This improved performance can be directly related to better‐matched modulus and coefficient of thermal expansion (CTE) of the PCB substrate to the chip (silicon). A more sophisticated model is under construction, where the time dependent material properties and non‐linear effects such as solder creep will be included.

Details

Circuit World, vol. 27 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 6 April 2012

Annapurna Addagarla and N. Siva Prasad

Out‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can cause…

Abstract

Purpose

Out‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip‐chip on board (FCOB).

Design/methodology/approach

A 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values.

Findings

The present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature.

Originality/value

The 3D finite element approach considering the elasto‐plastic and temperature‐dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip‐chip assembly has been suggested.

Details

Soldering & Surface Mount Technology, vol. 24 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 29 April 2014

Ping Yang, Xiusheng Tang, Yu Liu, Shuting Wang and Jianming Yang

The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong…

Abstract

Purpose

The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided.

Design/methodology/approach

The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed.

Findings

The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip.

Research limitations/implications

It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work.

Practical implications

It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data.

Originality/value

This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.

Details

Microelectronics International, vol. 31 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 August 1999

L. Alex Chen, Irene Sterian, Brian Smith and Damien Kirkpatrick

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process…

Abstract

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. They will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the future. The requirements for further CSP assembly studies will also be addressed in this paper.

Details

Soldering & Surface Mount Technology, vol. 11 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Content available
45

Abstract

Details

Microelectronics International, vol. 18 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 December 2004

Minna Arra, David Geiger, Dongkai Shangguan and Jonas Sjöberg

The surface mount technology (SMT) assembly process for 0.4 mm pitch chip scale package (CSP) components was studied in this work. For the screen printing process, the printing…

Abstract

The surface mount technology (SMT) assembly process for 0.4 mm pitch chip scale package (CSP) components was studied in this work. For the screen printing process, the printing performance of different solder pastes, aperture shapes and sizes was investigated. Square apertures and a fine particle size in the solder paste provided a better paste release. Besides optimising the printing process capability and minimizing the printing defects such as bridging and missing paste, the total volume of solder consisting of the paste and the solder ball has to be considered in order to maximize the final process yield. For the pick & place process, the accuracy required for the placement equipment was determined by studying the self‐alignment of the lead‐free CSPs (with Sn/4.0Ag/0.5Cu balls) during the reflow process using lead‐free Sn/3.9Ag/0.6Cu paste. The components were intentionally misplaced up to ∼50percent off‐pad. After reflow, x‐ray inspection showed that the components had aligned to the pad. By considering the stack‐up of the printed circuit board pad location and size tolerances, the solder paste printing tolerances and the placement tolerances, the required alignment accuracy for the pick & place equipment was established to meet the total process capability requirement.

Details

Soldering & Surface Mount Technology, vol. 16 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 December 2000

T.A. Nguty, N.N. Ekere, J.D. Philpott and G.D. Jones

High‐density packaging devices have unique characteristics which make their assembly, test and repair very difficult. The only realistic method of rework is to replace the…

Abstract

High‐density packaging devices have unique characteristics which make their assembly, test and repair very difficult. The only realistic method of rework is to replace the defective component with a new or re‐balled component. Although a wide range of rework techniques is available, degradation in assembly reliability may accompany the process. The formation of brittle secondary intermetallic compounds following CSP rework can adversely affect the mechanical properties of the joint, particularly when they make up a significant proportion of its thickness. Reports on the effects of different CSP rework techniques on intermetallic layer formation. Two PCB pad‐cleaning methods and three flux/paste deposition methods are investigated. The reworked joints are analysed using optical microscopy to determine the extent of intermetallic growth. Their quality is also assessed using shear strength testing prior to, and after, thermal ageing at 1008C to accelerate the growth of intermetallic compounds and evolution of the solder grain structure.

Details

Soldering & Surface Mount Technology, vol. 12 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 December 1997

J.H. Lau

The objective of this paper is to point out the limitations and ròles of DNP (distance to neutral point) on predicting the solder‐joint thermal‐fatigue life of area‐array…

444

Abstract

The objective of this paper is to point out the limitations and ròles of DNP (distance to neutral point) on predicting the solder‐joint thermal‐fatigue life of area‐array assemblies.

Details

Soldering & Surface Mount Technology, vol. 9 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 31 July 2007

Yung‐Hsiang Hung

The aim of this research is to combine the Taguchi method and hybrid methods of artificial intelligence, to use them as the optimal tool in wire bond designing parameters for an…

1330

Abstract

Purpose

The aim of this research is to combine the Taguchi method and hybrid methods of artificial intelligence, to use them as the optimal tool in wire bond designing parameters for an ultra‐thin chip scale package (CSP) package, and then construct a set of the optimal parameter analysis flow and steps.

Design/methodology/approach

The hybrid methodology of artificial Intelligence was used in order to identify the optimum parameters design for a wire bonding of ultra‐thin CSP package. This paper employed desirability function to integrate two quality characteristics (loop height and wire pull strength) into a single quality indicator to construct a well‐trained neural network prediction system with hybrid genetic algorithm.

Findings

The processes parameters of low‐loop of micro HDD driver IC were optimized with GA, thereby achieving the objective of improving process yield and robustness design of micro HDD driver IC.

Practical implications

The engineers could quickly obtain the optimal production process parameter with the demand of multi‐quality characteristics, and enhance the assembly quality and yield of driver IC of micro HDD.

Originality/value

This paper applies the design of experiments approach to a lower wire loop processes parameters design, and improves the process yield and robustness design of micro HDD driver IC.

Details

Microelectronics International, vol. 24 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

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