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Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS).

Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology.

Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption.

This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.

Nanopore-based molecular sensing and measurement, specifically DNA sequencing, is advancing at a fast pace. Some embodiments have matured from coarse particle counters to enabling full human genome assembly. This evolution has been powered not only by improvements in the sensors themselves, but also in the assisting microelectronic CMOS readout circuitry closely interfaced to them. In this light, this paper aims to review established and emerging nanopore-based sensing modalities considered for DNA sequencing and CMOS microelectronic methods currently being used.

Readout and amplifier circuits, which are potentially appropriate for conditioning and conversion of nanopore signals for downstream processing, are studied. Furthermore, arrayed CMOS readout implementations are focused on and the relevant status of the nanopore sensor technology is reviewed as well.

Ion channel nanopore devices have unique properties compared with other electrochemical cells. Currently biological nanopores are the only variants reported which can be used for actual DNA sequencing. The translocation rate of DNA through such pores, the current range at which these cells operate on and the cell capacitance effect, all impose the necessity of using low-noise circuits in the process of signal detection. The requirement of using in-pixel low-noise circuits in turn tends to impose challenges in the implementation of large size arrays.

The study presents an overview on the readout circuits used for signal acquisition in electrochemical cell arrays and investigates the specific requirements necessary for implementation of nanopore-type electrochemical cell amplifiers and their associated readout electronics.

The authors have analyzed IBM surveys on evolving C-suite technology priorities over several years to find fresh opportunities for Chief Executive Officers (CEOs), Chief Marketing Officers (CMOs) and Chief Information Officers (CIOs) to work closely together.

This new study of evolving technology priorities is based on conversations with thousands of private and public sector C-suite executives participating in a series of IBM surveys over the past decade.

The authors found that the major technology challenges facing corporations are how to manage openness across the organization, individualize customer relationships and invest in the partnership ecosystem for innovation.

This is a meta analysis based on a series of reports on IBM interviews with top executives starting in 2004.

To achieve significant innovation, outperforming organizations are pursuing external partnerships. Increasingly partners are non-traditional – communities of interest, academic institutions or other types of organizations.

The authors identify three key challenges for CEOs, CMOs and CIOs and show how they can align their technology plans and resources to address them.

Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.

In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.

The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.

The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.

SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.

The cell can be used for SRAM memory for low power consumptions.

The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

This paper explores the possible future business environment, industrial structure, technological transformation, and market for the semiconductor industry in Taiwan.

This study applies the Delphi method to predict future trends in Taiwan's semiconductor industry in 2015.

The significant findings are as follows: the future business environment will focus on “industrial internationalization” and “strategic alliance”, and roughly half of Taiwan's production will move to China by 2015; the disintegrated model in Taiwan's semiconductor industry will still remain by 2015 and will require some adjustments, whereas the foundry service in Taiwan will retain its dominance globally; future core technologies in 2015 will comprise low voltage manufacturing (CMOS), High K, nanotechnology processes, and copper interconnection processes; the estimated value of IC industrial production for 2005 was US$32.1 billion, and will be US$61.0 billion in 2010 and US$108.8 billion in 2015.

This research can be utilized as a reference for government, academics, industry, and international investors.

Researchers continue to seek understanding of industrialization as a state managed process. How to create and implement new industries based on advanced knowledge is on the policy agenda of many advanced nations. Measures that promote these developments include national capacity building in science and technology, the formation of technology transfer systems, and the establishment of industrial clusters. What these templates often overlook is an analysis of use. This chapter aims to increase the understanding of the processes that embed new solutions in structures from an industrial network perspective. The chapter describes an empirical study of high-technology industrialization in Taiwan that the researcher conducts to this end. The study shows that the Taiwanese industrial model is oversimplified and omits several important factors in the development of new industries. This study bases its findings on the notions that resource combination occurs in different time and space, the new always builds on existing resource structures, and the users are important as active participants in development processes.

Analog designers working infields such as aerospace, the defense and nuclear industries, telecommunications and medical electronics have long faced a special problem when trying to source application‐specific integrated circuits (ASICs) for their designs. Although digital ASICs have long been available with the degree of radiation hardening normally required for these applications, sourcing radiation‐hardened (‘rad‐hard’) analog ASICs has been much more difficult. In particular, the CMOS/SOS technology used very successfully to produce rad‐hard digital ASICs has long been considered to be fundamentally unsuitable for analog designs. Only now has CMOS/SOS technology been developed to the point where highly integrated, high‐performance rad‐hard analog ASICSs can be made readily available — thanks to a breakthrough by Swedish semiconductor specialists ABB HAFO that is now opening up new opportunities for analog designers everywhere.

The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper.

The design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz.

The maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power.

The PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.