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Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.

Gas thrust foil bearings (GTFBs) are used to balance the axial load of engines. However, in some working conditions of large axial force, such as the use of single impeller air compressor, the load capacity of GTFBs is still insufficient. To solve this problem, the load capacity can be improved by increasing the stiffness of bump foil. The purpose of this paper is to explore a scheme to effectively improve the performance of thrust foil bearings. In the paper, the stiffness of bump foil is improved by increasing the thickness of bump foil and using double-layer bump foil.

The foil deformation of GTFBs supported by three different types of bump foils, the relationship between friction power consumption and external force and the difference of limited load capacity were measured by experimental method.

The variation of the foil deformation, bearing stiffness, friction power consumption with the external force at different speeds and limited load capacity are obtained. Based on experimental results, the selection scheme of bump foil thickness is obtained.

This paper provides a feasible method for the performance optimization of GTFBs.

Sn‐Pb and Sn‐Ag bumps (130 μm diameter, 250 μm pitch) made using an electroplating process were studied. As a preliminary experiment, the effects of current density and plating time on the Sn‐Pb and Sn‐Ag deposits were investigated. The morphology and composition of the plated surface were examined using scanning electron microscopy. The shape and thickness of the solder bumps were also compared. Bump shear testing was performed to measure the adhesion strength between the solder bumps and the under bump metallurgy. In electroplating, the Sn‐Ag plating thickness was proportional to the current density, while plated Sn‐Pb thickness saturated above the limiting current density. The optimal conditions for solder bump fabrication were found at 6 A/dm² for 3 h in the case of Sn‐Pb bump plating and 6 A/dm² for 1 h for the Sn‐Ag bump plating. The bump shear strength for Sn‐Ag was found to be higher than that of Sn‐Pb.

Bumping is a prerequisite for flip‐chip attachment of bare dies. For silicon semiconductors bumping is normally performed on the ICs at wafer scale. Bumping can be performed by micro‐plating or vacuum deposition techniques. Mechanical methods are also well known. In this paper a bumping process based on tin/lead alloy plating is reported. The plating bath presented enables the deposition of both solder compositions used for flip‐chip attachment, the eutectic and the lead‐rich. All key issues of the plating process covering plating equipment, electrolyte characteristics and plating process parameters are discussed. Methods of bump characterisation and quality assurance are reported as an important part of the bumping process. The deciding process parameters leading to high quality solder bumps are demonstrated.

Indium solders are frequently used for interconnections in cooled systems because of their high ductility down to very low temperatures. Very fine contact pitches are required for hybrid mosaic radiation sensors compared with those for conventional flip‐chip technology. This paper presents solutions for bumping and bonding indium bumps based on the measured properties of indium solders in relation to the requirements of, and possibilities for, manufacture of fine pitch solder bump features.

Ball‐bumping is a flexible low cost bumping technology based on the conventional wire bonding procedure. It is applicable to single chips or whole wafers as well as to substrates. As established wire‐bonding machines can be used, expensive bumping‐process equipment for phototooling and plating is not necessary. Flip‐chip bonding is the most advantageous attach method of high frequency applications. Compared with wire‐bonding and TAB it allows the highest contact density, the shortest signal paths and lowest interconnection parasitics. The reduced pad sizes and pitches, not only of GaAs devices, demand a well controlled bump deformation during flip‐chip bonding. This work develops process parameters for the flip‐chip bonding of silicon and GaAs devices with respect to the best interconnection result by lowest bonding force and ball‐bump deformation. Ball‐bumps with diameters of 50 and 80 urn (2.0 and 3.2 mils) were created using 98% AuPd bump wire with diameters of 18 µm (0.7 mil) and 25 µm (1.0 mil) respectively. Ball‐bumping with a minimal pitch of 70 µm (2.8 mils) has been achieved. A special preparation allowed the shear test investigation of each bump/pad interface after flip‐chip attach. Bonding forces of 20 and 25 cN/bump respectively lead to a good welding in the bump/substrate interface due to the special shape of ball‐bumps. For silicon devices which have a pad metallisation of aluminium, the shear forces of the bump/pad interface increase after flip‐chip bonding, too. No cratering of GaAs and silicon occurs after flip‐chip bonding due to a low bonding force ramp of 5 cN/s and 10 cN/s respectively. The flip‐chip attach of a Fujitsu FLR 016 GaAs‐FET which has pad sizes of 35 urn is demonstrated. In this case, substrate bumping is the more advantageous bumping method. The feasibility of fine‐pitch TAB attach using ball‐bumps is introduced. 100 µm (3.9 mils) pitch silicon devices with 328 pads were ball‐bumped for both solder and thermal‐compression TAB. Bond forces were in the range of 9–11 cN/bump and 15–21 cN/bump respectively. Pull forces of approximately 30 cN/lead show good results of the bump/lead interconnection after TAB.

Tape automated bonding (TAB) is a suitable technology for assembling ICs with a high number of l/Os. The gang bonding process usually applied requires increasing thermode forces for chips with high lead counts and narrow tolerances regarding thermode parallelism and planarity. Due to the high bonding pressure, TC bonding of Au bumps to Au‐plated tapes becomes critical for these applications. In order to avoid damage to the pad structure an inner lead bonding (ILB) process with reduced pressure is required. A tape metallisation of 0.5–1.0 µm Sn is not sufficient for a significant reduction of thermode pressure. As an alternative, the application of an eutectic Au‐Sn cushion which is deposited on top of the bumps is presented. A modified bumping process was developed for the deposition of the solder bumps. Soldering of the Au‐Sn bumps to a Au‐plated tape was performed successfully by two techniques: thermode gang bonding and laser soldering. Bond parameters and tin layer thickness were optimised. Reliability investigations by thermal ageing were performed. The special metallurgical aspects of the system were investigated with a microprobe.

Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h).

The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on.

It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad.

In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.

This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

The impact strength of solder joint under high strain rate was evaluated by board level test method. However, the impact shear test of single solder bump was more convenient and economical than the board level test method. With the miniaturization of solder joints, solder joints were more prone to failure under thermal shock and more attention has been paid to the impact reliability of solder joint. But Pb-free solder joints may be paid too much attention and Sn-Pb solder joints may be ignored.

In this study, thermal shock test between −55°C and 125°C was conducted on Sn-37Pb solder bumps in the BGA package to investigate microstructural evolution and growth mechanism of interfacial intermetallic compounds (IMCs) layer. The effects of thermal shock and ball diameter on the mechanical property and fracture behavior of Sn-37Pb solder bumps were discussed.

With the increase of ball size, the same change tendency of shear strength with thermal shock cycles. The shear strength of the solder bumps was the highest after reflow; with the increase of the number of thermal shocks, the shear strength of the solder bumps was decreased. But at the time of 2,000 cycles, the shear strength was increased to the initial strength. Minimum shear strength almost took place at 1,500 cycles in all solder bumps. The differences between maximum shear strength and minimum shear strength were 9.11 MPa and 16.83 MPa, 17.07 MPa and 15.59 MPa in φ0.3 mm and φ0.4 mm, φ0.5 mm and φ0.6 mm, respectively, differences were increased with increasing of ball size. With similar reflow profile, the thickness of IMC decreased as the diameter of the ball increased. The thickness of IMC was 2.42 µm and 2.17 µm, 1.63 µm and 1.77 µm with increasing of the ball size, respectively.

Pb-free solder was gradually used to replace traditional Sn-Pb solder and has been widely used in industry. Nevertheless, some products inevitably used a mixture of Sn-Pb and Pb-free solder to make the transition from Sn-Pb to Pb-free solder. Therefore, it was very important to understand the reliability of Sn-Pb solder joint and more further research works were also needed.