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The submitted paper is mainly concerned with the cracking of blind and buried vias of printed circuit board (PCB) for smartphones which were encountered with abnormal display problems like scramble display or no display during service and had to be recalled.

To found out the root causes of this failure and dissolve this commercial dispute, comprehensive failure analysis was performed on the printed circuit board assemblies (PCBAs) and PCBs of the failed smartphone, such as macrograph and micrograph observation, chemical compositions analysis, thermal performance testing and blind via pull-off experiment, which finally helped to determine the causes. Besides that, the failure mechanisms were discussed in detail, and pertinent countermeasures were proposed point by point.

It was found that the PCB blind vias cracking was the main reason for the scramble display or no display of the smartphone, and the incomplete cleaning process before copper plating was the root cause of the blind vias cracking.

Achievement of this paper would not only help to provide the solid evidence for determining the responsibility of this commercial dispute but also lead to a better understanding of the failure mechanisms and prevention methods for similar failure cases of other advanced mobile phones.

Most failure analysis researches of PCBAs only focused on the unqualified products from manufacturing, while this paper addressed a failure analysis case of PCBAs products for smartphones from actual services, which was relatively rarely reported in the past.

The submodeling technique is incorporated in a finite element analysis to investigate the stress state of blind vias of different structural configurations.

The test vehicle is a multi‐chip module plastic ball grid array comprised of a four‐layer build‐up substrate. The calculated displacement field from the global model for the entire package is interpolated on the boundaries of the submodel, which involved the detailed structure of a blind via structure. Through the analysis, the potential of fracturing on the blind via is examined.

From the analysis it was found that filled blind vias in general have a smaller potential for delamination compared to the unfilled ones. Moreover, symmetric blind via layouts with a blind via located at the center of the through hole appear to be the most appropriate design for this particular test vehicle.

The value of the paper lies in its ability to provide insights into the prevention of fracturing of blind vias in a build‐up substrate through a novel numerical analysis using the submodeling technique.

With SMD‐Technology, the first purpose of plated‐through holes—to fix the components to the board—is no longer relevant. The utilisation of blind vias, preferably in combination with buried vias, results in an extremely high interconnection and packaging density and in most cases in fewer signal layers. Technology problems like drilling with precisely controlled Z‐axis as well as through‐plating of blind vias have been overcome. Reliability tests have shown a substantially lower failure rate in thermal cycling tests for DENSTRATE® multilayers.

The tenting of via holes has been a controversial issue in the military arena for several years. This issue has gained importance with MIL‐STD‐2000's requirement that all circuitry and vias under components be coated to preclude entrapment of flux. This paper addresses this issue by evaluating the MIL‐Spec thermal shock reliability of solder mask as a hole fill material and as a via tent cover. The relationship of via hole to pad size on tent reliability and solder mask thickness is also investigated. This paper concludes that solder mask as a hole fill material will not pass military thermal shock requirements and that standard dry film solder mask is very sensitive to via hole and pad dimensions. The thinner and more flexible high conformance solder mask is the only material capable of passing MIL‐Spec thermal shock requirements for all via hole to pad relationships.

The purpose of this paper is to present the materials and process considerations and solutions that enable the safe use of plugging pastes in high density interconnection (HDI) printed circuit boards (PCBs) designed to operate at higher temperatures.

The paper introduces the concept of microvia plugging and the issues that are important in influencing HDI PCB reliability. Plugging pastes and their properties are discussed along with the various plugging processes that can be used. The advantages and disadvantages of each type of process are compared and contrasted.

The creation of via holes and the filling of these interconnection holes or buried vias and their subsequent copper plating is one of the key processes in HDI technology. In future, the importance of plugging will increase, particularly on account of the growing demand for copper plating and dimensional stability.

The paper highlights the importance of making the correct selection of materials and processing methodologies and details the implications of these choices.

The paper describes the different approaches that can be used for filling microvias and details the issues, advantages and disadvantages of the various approaches. The paper particularly focuses on the special demands on plugging pastes used in higher temperature range applications.

Focuses on the development and capabilities of interconnect stress testing (IST), a stress testing method for printed circuit boards (PCBs) that is fast, repeatable and reproducible. IST technology was originally developed in the mid 1980s. Notes that using IST as an electrical test delivers a capability to remove the human factor from the decision making process of product acceptance or rejection and that the technology is emerging as an important test methodology for the assessment of PCB interconnects. IST has the capability to effectively and rapidly quantify the integrity of plated through holes and the unique ability to identify the presence and levels of post separations within a multilayer board.

Emerging ‘chip‐size’ packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages, including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.

The purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures.

Microvia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing.

Single and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs.

This work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations.

This paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.

In the past three years, microvia drilling using laser technology has become the dominant method of producing blind vias smaller than 150μm. The ablation characteristics of the materials used in the manufacture of PWBs can be divided into three categories: organics, glass, and metals. Organics are composed of resins and epoxies commercially available from a variety of vendors. Two types of resins that are typically used for microvia formation in the telecommunication applications are resin coated copper foil^® (RCC or RCF) for subtractive PCB process, and thermal‐curing resin (TCR) for additive PCB process respectively. This paper details the basics of UV YAG laser capabilities, alignment techniques, plating tests, reliability tests, manufacturable microvia design rules, and production experiences.

The purpose of this paper is to discuss the use of epoxy‐based conducting adhesives in z‐axis interconnections.

A variety of conductive adhesives with particle sizes ranging from 80 nm to 15 μm were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the micro‐structures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90° peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IR‐reflow, thermal cycling, pressure cooker test (PCT), and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling (DTC) between −55 and 125°C.

The volume resistivity of copper, silver and low‐melting point (LMP) alloy based paste were 5 × 10⁻⁴, 5 × 10⁻⁵ and 2 × 10⁻⁵ Ω cm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTC‐treated Cu as high as 2.75 lbs/in. for silver, and as low as 1.00 lb/in. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600 ψ, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IR‐reflow, PCT, and solder shock. Among all, silver‐based adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silver‐filled paste decreased due to sintering of metal particles.

As a case study, an example of silver‐filled conductive adhesives as a z‐axis interconnect construction for a flip‐chip plastic ball grid array package with a 150 μm die pad pitch is given.

A high‐performance Z‐interconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multi‐chip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.