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Article
Publication date: 1 January 2024

Rilwan Kayode Apalowo, Mohamad Aizat Abas, Muhamed Abdul Fatah Muhamed Mukhtar, Fakhrozi Che Ani and Mohamad Riduwan Ramli

This study aims to investigate the reliability issues of microvoid cracks in solder joint packages exposed to thermal cycling fatigue.

Abstract

Purpose

This study aims to investigate the reliability issues of microvoid cracks in solder joint packages exposed to thermal cycling fatigue.

Design/methodology/approach

The specimens are subjected to JEDEC preconditioning level 1 (85 °C/85%RH/168 h) with five times reflow at 270°C. This is followed by thermal cycling from 0°C to 100°C, per IPC-7351B standards. The specimens' cross-sections are inspected for crack growth and propagation under backscattered scanning electronic microscopy. The decoupled thermomechanical simulation technique is applied to investigate the thermal fatigue behavior. The impacts of crack length on the stress and fatigue behavior of the package are investigated.

Findings

Cracks are initiated from the ball grid array corner of the solder joint, propagating through the transverse section of the solder ball. The crack growth increases continuously up to 0.25-mm crack length, then slows down afterward. The J-integral and stress intensity factor (SIF) values at the crack tip decrease with increased crack length. Before 0.15-mm crack length, J-integral and SIF reduce slightly with crack length and are comparatively higher, resulting in a rapid increase in crack mouth opening displacement (CMOD). Beyond 0.25-mm crack length, the values significantly decline, that there is not much possibility of crack growth, resulting in a negligible change in CMOD value. This explains the crack growth arrest obtained after 0.25-mm crack length.

Practical implications

This work's contribution is expected to reduce the additional manufacturing cost and lead time incurred in investigating reliability issues in solder joints.

Originality/value

The work investigates crack propagation mechanisms of microvoid cracks in solder joints exposed to moisture and thermal fatigue, which is still limited in the literature. The parametric variation of the crack length on stress and fatigue characteristics of solder joints, which has never been conducted, is also studied.

Details

Soldering & Surface Mount Technology, vol. 36 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 11 May 2023

Mohammad A. Gharaibeh and James M. Pitarresi

Because of growing demand for slim, thin and cheap handheld devices, reduced-volume solder interconnects like land grid array (LGA) are becoming attractive and popular choices…

Abstract

Purpose

Because of growing demand for slim, thin and cheap handheld devices, reduced-volume solder interconnects like land grid array (LGA) are becoming attractive and popular choices over the traditional ball grid array (BGA) packages. This study aims to investigate the mechanical shock and impact reliability of various solder alloys and BGA/LGA interconnect configurations.

Design/methodology/approach

Therefore, this paper uses drop testing experiments and numerical finite element simulations to evaluate and compare the reliability performance of both LGA and BGA components when exposed to drop and impact loadings. Additionally, three common solder alloys, including 63Sn37Pb, SAC305 and Innolot, are discussed.

Findings

The results of this study showed that electronic packages’ drop and impact reliability is strongly driven by the solder configuration and the alloy type. Particularly, the combination of stiff solder alloy and shorter joint, LGA’s assembled with SAC305, results in highly improved drop reliability. Moreover, the BGA packages’ performance can be considerably enhanced by using ductile and compliant solder alloys, that is, 63Sn37Pb. Finally, this paper discussed the failure mode of the various solder configurations and used simulation results to explain the crack and failure situations.

Originality/value

In literature, there is a lack of published work on the drop and impact reliability evaluation and comparison of LGA and BGA solders. This paper provides quantitative analysis on the reliability of lead-based and lead-free solders when assembled with LGA and BGA interconnects.

Details

Soldering & Surface Mount Technology, vol. 35 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 12 September 2023

Zhili Zhao, Mingqiang Zhang, Xi Meng, Zhenkun Li, Jiazhe Li, Luying Qiu and Zeyu Ren

The author proposed a friction plunge micro-welding (FPMW) method and applied it to column grid array packaging to realize the connection of copper columns without precision molds…

Abstract

Purpose

The author proposed a friction plunge micro-welding (FPMW) method and applied it to column grid array packaging to realize the connection of copper columns without precision molds assisted positioning. The purpose of this paper is to study the flow behavior of the solder undergoing frictional thermo-mechanical action during the FPMW and to determine the source of the solders in the micro-zones with different microstructure characteristics near the solder/Cu column friction interface.

Design/methodology/approach

Three kinds of Sn58Bi/SAC305 and SAC305/Pb90Sn composite solder samples were designed to study the flow behavior of the solder during FPMW using Bi and Pb as tracer elements.

Findings

The results show that most of the solders in the position occupied by the copper column was softened and plasticized during the welding process and was extruded to side of the copper column, flowing axially, circumferentially and radially along a trajectory similar to a conical spiral line. Under the drive of the tangential friction force and the radial hold-tight force, the extruded out visco-plastic solders fully mixed with the visco-plastic solders on the sides of the copper column, and bonded with the solders that deformed plastically on the periphery, so that a stir zone and a dynamic recrystallization zone finally evolved. The outside plastically deformed solders evolved into a thermo-mechanical affected zone.

Originality/value

The flow behavior of the solder during the FPMW was determined, as well as the source of the solders in micro-zones with different microstructure characteristics.

Details

Soldering & Surface Mount Technology, vol. 36 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 31 January 2024

Zhenkun Li, Zhili Zhao, Jinliang Liu and Xin Ding

To solve the problems caused by using precise molds for copper column positioning in the current column grid array package, this paper aims to optimize the proposed friction…

Abstract

Purpose

To solve the problems caused by using precise molds for copper column positioning in the current column grid array package, this paper aims to optimize the proposed friction plunge micro-welding (FPMW) technology without mold assistance, to overcome the problems of low interfacial bonding strength, shrinkage cavities and flash defects caused by the low hold-tight force of solder on the copper column.

Design/methodology/approach

A pressurizing device installed under the drill chuck of the friction welding machine is designed, which is used to apply a static constraint to the solder ball obliquely downward to increase the hold-tight force of the peripheral solder on the copper column during welding and promote the friction metallurgical connection between them.

Findings

The results show that the application of static constraint during welding can increase the compactness of the solder near the friction interface and effectively inhibit occurrences of flash, shrinkage cavities and crystal defects such as vacancies. Therefore, compared with the unconstrained (UC) FPMW, the average strength of the statically constrained (SC) FPMW joints and aged SC-FPMW joints can be increased by 51.1% and 122.6%, and the problem of the excessive growth of the interfacial connection layer in the UC-FPMW joints during aging can be effectively avoided.

Originality/value

The application of static constraint effectively inhibits the occurrence of defects such as shrinkage cavities, vacancies and flash in FPMW joints, and the welding quality is significantly improved.

Details

Soldering & Surface Mount Technology, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 24 October 2023

Calvin Ling, Muhammad Taufik Azahari, Mohamad Aizat Abas and Fei Chong Ng

This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.

Abstract

Purpose

This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.

Design/methodology/approach

A set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter.

Findings

All findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain.

Practical implications

This study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill.

Originality/value

The void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement.

Details

Soldering & Surface Mount Technology, vol. 36 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 28 July 2023

Mohammad A. Gharaibeh

This paper aims to compare and evaluate the influence of package designs and characteristics on the mechanical reliability of electronic assemblies when subjected to harmonic…

Abstract

Purpose

This paper aims to compare and evaluate the influence of package designs and characteristics on the mechanical reliability of electronic assemblies when subjected to harmonic vibrations.

Design/methodology/approach

Using finite element analysis (FEA), the effect of package design-related parameters, including the interconnect array configuration, i.e. full vs perimeter, and package size, on solder mechanical stresses are fully addressed.

Findings

The results of FEA simulations revealed that the number of solder rows or columns available in the array, could significantly affect solder stresses. In addition, smaller packages result in lower solder stresses and differing distributions.

Originality/value

In literature, there are no papers that discuss the effect of solder array layout on electronic packages vibration reliability. In addition, general rules for designing electronic assemblies subjected to harmonic vibration loadings are proposed in this paper.

Details

Microelectronics International, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 10 October 2023

Xiao He, Lijuan Huang, Meizhen Xiao, Chengyong Yu, En Li and Weiheng Shao

The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the…

Abstract

Purpose

The purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.

Design/methodology/approach

The approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.

Findings

To meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.

Originality/value

The PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.

Details

Microelectronics International, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 31 May 2023

Songtao Qu and Qingyu Shi

In the electronic assembly industry, low-temperature soldering holds great potential to be used in surface mounting technology. Tin–bismuth (Sn–Bi) eutectic alloys are lead-free…

Abstract

Purpose

In the electronic assembly industry, low-temperature soldering holds great potential to be used in surface mounting technology. Tin–bismuth (Sn–Bi) eutectic alloys are lead-free solders applied in consumer electronics because of their low melting point, high strength and low cost. This paper aims to investigate how to address the problem of hot tear crack formation during Sn–Bi low-temperature solder (LTS) in the mass production of consumer electronics.

Design/methodology/approach

This paper explored the development of hot tear cracks during Sn–Bi soldering in the fabrication of flip chip ball grid arrays. Experiments were designed to simulate various conditions encountered in Sn–Bi soldering. Quantitative analysis was conducted on the number of hot tear cracks observed in different alloy compositions and solder volumes to explore the primary cause of hot tear cracks and possible methods to suppress crack formation.

Findings

Hot tear cracks existed in Sn–Bi solders with different bismuth (Bi) contents, but increasing the solder volume reduced the number of hot tear cracks. Experiments were designed to test the degree of chip transient thermal warpage with temperature change, and, according to the results, glue was dispensed in specific areas to reduce chip warpage deformation. Finally, the results of combined process experiments pointed to an effective method of low-temperature soldering to suppress hot tear cracks.

Research limitations/implications

The study focuses on Sn–Bi solders only without other solder pastes such as SAC305 or Sn–Zn series.

Practical implications

With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles electronics, solar photovoltaic and other field, there will be more and more demand for low- temperature, energy-saving, lead-free solders. Therefore, this study will help the industry to roll out LTS (Sn–Bi) solutions rapidly.

Social implications

In the long term, lean and green manufacturing is expected to be essential for maintaining an advanced manufacturing industry across the world. Developing new LTSs and soldering processes is the most effective, direct solution for energy conservation and emission mitigation. With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles and solar photovoltaics, there would be an increased demand for low-temperature, energy-saving, lead-free techniques.

Originality/value

Although there are many methods that can be used to suppress hot tear cracks, there is little research on how to control the hot tear cracks caused by the low-temperature soldering of Sn–Bi in laptop applications. The authors studied the hot tear cracks that developed during the world’s first mass production of 50 million personal laptops based on low-temperature Sn–Bi alloy solder pastes. By controlling the Bi content, redesigning the solder paste printing process (e.g. through a printer’s stencil) and adding dispensing processes, the authors obtained reliable and stable experimental data and conclusions.

Details

Soldering & Surface Mount Technology, vol. 35 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 6 September 2021

Chun Hei Edmund Sek, M.Z. Abdullah, Kok Hwa Hwa Yu and Shaw Fong Wong

This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage…

Abstract

Purpose

This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.

Design/methodology/approach

This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.

Findings

Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.

Research limitations/implications

The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.

Practical implications

This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.

Social implications

The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.

Originality/value

The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

Details

Circuit World, vol. 49 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 4 December 2023

Yang Liu, Xin Xu, Shiqing Lv, Xuewei Zhao, Yuxiong Xue, Shuye Zhang, Xingji Li and Chaoyang Xing

Due to the miniaturization of electronic devices, the increased current density through solder joints leads to the occurrence of electromigration failure, thereby reducing the…

44

Abstract

Purpose

Due to the miniaturization of electronic devices, the increased current density through solder joints leads to the occurrence of electromigration failure, thereby reducing the reliability of electronic devices. The purpose of this study is to propose a finite element-artificial neural network method for the prediction of temperature and current density of solder joints, and thus provide reference information for the reliability evaluation of solder joints.

Design/methodology/approach

The temperature distribution and current density distribution of the interconnect structure of electronic devices were investigated through finite element simulations. During the experimental process, the actual temperature of the solder joints was measured and was used to optimize the finite element model. A large amount of simulation data was obtained to analyze the neural network by varying the height of solder joints, the diameter of solder pads and the magnitude of current loads. The constructed neural network was trained, tested and optimized using this data.

Findings

Based on the finite element simulation results, the current is more concentrated in the corners of the solder joints, generating a significant amount of Joule heating, which leads to localized temperature rise. The constructed neural network is trained, tested and optimized using the simulation results. The ANN 1, used for predicting solder joint temperature, achieves a prediction accuracy of 96.9%, while the ANN 2, used for predicting solder joint current density, achieves a prediction accuracy of 93.4%.

Originality/value

The proposed method can effectively improve the estimation efficiency of temperature and current density in the packaging structure. This method prevails in the field of packaging, and other factors that affect the thermal, mechanical and electrical properties of the packaging structure can be introduced into the model.

Details

Soldering & Surface Mount Technology, vol. 36 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

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