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Article
Publication date: 26 July 2013

Chun‐Sean Lau, M.Z. Abdullah and C.Y. Khor

Reflow soldering is one of the most significant factors in determining solder joint defect rate. This study aims to introduce an innovative approach for optimizing the multiple…

Abstract

Purpose

Reflow soldering is one of the most significant factors in determining solder joint defect rate. This study aims to introduce an innovative approach for optimizing the multiple performances of the reflow soldering process.

Design/methodology/approach

This study aims to minimize the solder joint defect rate of a ball grid array (BGA) package by using the grey‐based Taguchi method. The entropy measurement method was employed together with the grey‐based Taguchi method to compute for the weights of each quality characteristic. The Taguchi L18 orthogonal array was performed, and the optimal parameter settings were determined. Various factors, such as slope, temperature, and reflow profile time, as well as two extreme noise factors, were considered. The thermal stress, peak temperature, reflow time, board‐ and package‐level temperature uniformity were selected as the quality characteristics. These quality characteristics were determined using the numerical method. The numerical method comprises the internal computational flow that models the reflow oven coupled with the structural heating and cooling models of the BGA assembly. The Multi‐physics Code Coupling Interface was used as the coupling software.

Findings

The analysis of variance results reveals that the cooling slope was the most influential factor among the multiple quality characteristics, followed by the soaking temperature and the peak temperature. Experimental confirmation test results show that the performance characteristics improved significantly during the reflow soldering process.

Practical implications

The proposed approach greatly reduces solder joint defects and enhances solutions to lead‐free reliability issues in the electronics manufacturing industry.

Originality/value

The findings provide new guidelines to the optimization method which are very useful for the accurate control of the solder joint defect rate within components and printed circuit board (PCB) which is one of the major requirements to achieve high reliability of electronic assemblies.

Article
Publication date: 6 April 2012

Chun‐Sean Lau, M.Z. Abdullah and F. Che Ani

The purpose of this paper is to develop a thermal coupling method of a ball grid array (BGA) assembly during a forced convection reflow soldering process.

Abstract

Purpose

The purpose of this paper is to develop a thermal coupling method of a ball grid array (BGA) assembly during a forced convection reflow soldering process.

Design/methodology/approach

The reflow oven was modeled in computational fluid dynamic (CFD) software (FLUENT 6.3.26) while the structural heating BGA package simulation was done using finite element method (FEM) software (ABAQUS 6.9). Both software applications were coupled bi‐directionally using the code coupling software MpCCI.

Findings

The convective heat transfer coefficient (h) simulated during the reflow process showed a sufficient view of the changing h in the BGA assembly of each reflow oven. The solder joints were found to experience phase change from solid to liquid during heating and liquid to solid during cooling. These phase changes were present at the melting temperature of the solder joint. The effect of the phase transition point was to cause a large range of temperature difference within the BGA assembly. This situation runs the risk of a skewing defect of components. The simulation results were compared with the experimental results and found to be in good conformity. In addition, the maximum thermal stress from simulation results was trapped in the interfaces between the solder joints and substrate, which tended to form the nucleation of initial crack.

Practical implications

The current study provides a methodology for designing a thermal profile for reflow soldering production.

Originality/value

The findings provide new guidelines for the thermal coupling method. This guideline is very useful for the accurate control of temperature distributions within components and printed circuit boards, which is one of major requirements for achieving high reliability in electronic assemblies.

Details

Soldering & Surface Mount Technology, vol. 24 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 4 April 2016

Chun Sean Lau, C.Y. Khor, D. Soares, J.C. Teixeira and M.Z. Abdullah

The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review…

1034

Abstract

Purpose

The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.

Design/methodology/approach

Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.

Findings

With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.

Practical implications

This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.

Originality/value

The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

Details

Soldering & Surface Mount Technology, vol. 28 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 February 1994

J. Lau, J. Miremadi, J. Gleason, R. Haven, S. Ottoboni and S. Mimura

A no‐clean mass reflow process for 396‐pin, 324‐pin and 225‐pin over moulded plastic pad array carriers (OMPACs) or plastic ball grid array (BGA) is presented. Emphasis is placed…

Abstract

A no‐clean mass reflow process for 396‐pin, 324‐pin and 225‐pin over moulded plastic pad array carriers (OMPACs) or plastic ball grid array (BGA) is presented. Emphasis is placed on the OMPAC assembly parameters such as the design, material and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass re‐flow and inspection. Furthermore, cross‐sections and the ‘popcorn’ effect of the OMPAC assembly are provided and discussed.

Details

Circuit World, vol. 20 no. 3
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 1 August 1999

L. Alex Chen, Irene Sterian, Brian Smith and Damien Kirkpatrick

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process

Abstract

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. They will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the future. The requirements for further CSP assembly studies will also be addressed in this paper.

Details

Soldering & Surface Mount Technology, vol. 11 no. 2
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 18 January 2013

Yap Boon Kar, Noor Azrina Talik, Zaliman Sauli, Jean Siow Fei and Vithyacharan Retnasamy

The increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder…

Abstract

Purpose

The increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.

Design/methodology/approach

This paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.

Findings

It is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.

Originality/value

The paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.

Details

Microelectronics International, vol. 30 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 June 1999

John H. Lau, Tony Chen and Tai‐Yu Chou

A family of cavity‐down plastic ball grid array (PBGA) packages have been designed by split via connection (SVC) and split wrap around (SWA) methods. Because of the special…

Abstract

A family of cavity‐down plastic ball grid array (PBGA) packages have been designed by split via connection (SVC) and split wrap around (SWA) methods. Because of the special designs, these packages consist of a single core of organic material and two‐metal layers of copper and are manufactured with the conventional printed circuit board (PCB) process at very low cost. The electrical performances of the packages are studied by both numerical simulations and experimental measurements. Parasitic parameters are extracted from time domain reflectometer (TDR) and time domain transmission (TDT) measurements. Cross‐talk and simultaneous switch output (SSO) noise of the packages are also investigated.

Details

Circuit World, vol. 25 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 April 1989

J. Adams

Solder quality is a critical issue in circuit board production. However, the manufacturing process of today has few built‐in controls to ensure good solder quality. Instead…

Abstract

Solder quality is a critical issue in circuit board production. However, the manufacturing process of today has few built‐in controls to ensure good solder quality. Instead, attention is only paid when a defect is found. The solution lies in the integration of inspection, test and process control. Now a new method, Scanned‐Beam Laminography, takes 3‐dimensional X‐ray slices of solder joints, enabling thorough inspection of each joint. Special software algorithms measure and report the solder joint conditions, creating a system which provides real‐time process control.

Details

Circuit World, vol. 16 no. 1
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 27 May 2014

Weisheng Xia, Ming Xiao, Yihao Chen, Fengshun Wu, Zhe Liu and Hongzhi Fu

– The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

Abstract

Purpose

The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

Design/methodology/approach

A thermal-mechanical coupling method that used finite-element method software (ANSYS 13.1) was performed. Meanwhile, a shadow moiré apparatus (TherMoiré PS200) combined with a heating platform was used for the experimental measurement of the warpage of PBGA according to the JEDEC Standard.

Findings

The authors found that the temperature profiles taken from the simulated results and experimental measurement are consistent with each other, only with a little and acceptable difference in the maximum temperatures. Furthermore, the maximum warpage measurements during the reflow process are 0.157 mm and 0.149 mm for simulation and experimental measurements, respectively, with a small 5.37 per cent difference. The experimental measurement and simulated results are well correlated. Based on the validated finite element model, two factors, namely, the thickness and dimension of PCB, are explored about their effect on the thermal warpage of PBGA mounted on PCB during the reflow process.

Practical implications

The paper provides a thorough parametrical study of the thermal warpage of PBGA mounted on PCB during the reflow process.

Originality/value

The findings in this paper illustrate methods of warpage study by combination of thermal-mechanical finite element simulation and experimental measurement, which can provide good guidelines of the PCB design in the perspective of thermal warpage during the reflow process.

Details

Soldering & Surface Mount Technology, vol. 26 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 January 1984

G. Kersuzan, Nigel Batt, Brian Waterfield, Hamish Law, B. Herod, M.A. Whiteside and Nihal Sinnadurai

The International Electronic Components Show in Paris in November, 1983, provided the occasion for a very successful meeting of ISHM‐France which attracted 170 attendees. The…

Abstract

The International Electronic Components Show in Paris in November, 1983, provided the occasion for a very successful meeting of ISHM‐France which attracted 170 attendees. The following presentations were given:

Details

Microelectronics International, vol. 1 no. 4
Type: Research Article
ISSN: 1356-5362

1 – 10 of 188