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The role of the physiotherapist's services in the fracture clinic was audited to evaluate whether the number of treatments required by the patients was reduced, whether waiting time for an appointment was reduced, and patients' views of the physiotherapy services in the fracture clinic.

The first phase of this study developed a multi‐professionally agreed list of adverse events for clinical incident reporting in Trauma and Orthopaedics. This follow‐up study aims to evaluate the effectiveness of the adverse event list.

Two follow‐up questionnaires were sent to healthcare professionals working in Trauma and Orthopaedics in two of the participating National Health Service (NHS) Trusts (n=247 for the first questionnaire and n=240 for the second questionnaire). Trends in routine incident reporting data were also monitored over a two‐year period to determine the impact of the adverse event list on levels of adverse event reporting.

The questionnaires indicated that awareness about the adverse event list was good and improved between questionnaires. However usage of the adverse event list appeared to be poor. Multiple regression analysis with the dependent variable count of orthopaedic incidents suggested that the adverse event list had little, if any impact on levels of reporting in Trauma and Orthopaedics.

The results of this study suggest that a practical tool, such as the adverse event list has little impact on incident reporting levels.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

The purpose of this paper is to analyze the effect of driver size and number of shells on propagation delay and power for multi‐walled carbon nanotubes (MWCNT) interconnects at 22 nm technology node.

An equivalent circuit model of MWCNT is used for estimation and analysis of propagation delay and power. The delay and power through MWCNT and Cu interconnects are compared for various driver sizes and number of MWCNT shells.

The SPICE simulation results show that the MWCNT interconnect has lower propagation delay than Cu interconnects. The delay ratio of MWCNT to Cu decreases with increase in length for different driver size and number of MWCNT shells. However, the delay ratio increases with reduction in number of MWCNT shells. The ratio of average power consumption (MWCNT/Cu) also decreases with the variation in driver size and numbers of shells with respect to the length of interconnect. The theoretical study proves CNTs to be better alternatives against copper on the ground of performance parameters.

Several challenges remain to be overcome in the areas of fabrication and process integration for CNTs. Lowering of metal nanotube contact resistance would be vital, especially for local interconnect and via applications. Moreover, rigorous characterization and modeling of electromagnetic interactions in CNT bundles; 3‐D (metal) to 1‐D (CNT) contact resistance; impact of defects on electrical and thermal properties; and high‐frequency effects are being seen as additional challenges.

This paper investigates, assesses and compares the performance of carbon nanotubes (CNT) based interconnects as prospective alternatives to copper wire interconnects in future VLSI chips. Multi walled CNTs assure for long/global interconnect applications.

In India, the COVID-19 outbreak has been declared an epidemic in all its states and union territories. To combat COVID-19, lockdown was imposed on March 25, 2020 which has adversely affected the education system in the country. It has changed the traditional education system to the educational technologies (EdTechs) model, where teaching and assessments are conducted online. This paper aims to identify the barriers faced by teachers during online teaching and assessment in different home environment settings in India.

Interpretative phenomenological analysis (IPA) of qualitative research methodology has been used in this research. The study was conducted among the teachers working in the government and private universities of Uttarakhand, India. Semi-structured in-depth interviews were conducted among 19 teachers to collect data regarding the barriers faced by them during online teaching and assessment. ATLAS.ti, version 8 was used to analyze the interview data.

The findings revealed four categories of barriers that are faced by teachers during online teaching and assessments. Under home environment settings, a lack of basic facilities, external distraction and family interruption during teaching and conducting assessments were major issues reported. Institutional support barriers such as the budget for purchasing advanced technologies, a lack of training, a lack of technical support and a lack of clarity and direction were also reported. Teachers also faced technical difficulties. The difficulties were grouped under a lack of technical support, it included a lack of technical infrastructure, limited awareness of online teaching platforms and security concerns. Teachers’ personal problems including a lack of technical knowledge, negative attitude, course integration with technology and a lack of motivation are identified as the fourth category to damper their engagement in online teaching and assessments.

The findings of the study can be helpful to the regulatory authorities and employers of higher education institutions who are planning to adopt online teaching as a regular activity in the future. The insights gained from the findings can help them to revisit their existing policy frameworks by designing new strategies and technical structures to assist their teachers in successfully embracing the EdTech to deal with any crisis in the future.

Many authors have conducted research to address the problems faced by students related to online teaching and learning during COVID-19 in India. To the best of the authors’ knowledge, this is the first study that addresses the challenges faced by teachers during the online teaching and assessment in the home environment settings by using qualitative analysis (IPA) techniques. The current study replenishes the gap by contributing to the literature of online teaching and assessment under the home environment settings during the pandemic situation.

To study the effect of voltage‐scaling on output voltage waveform, delay and power dissipation in a single inverter/repeater driven interconnect load, in different technology nodes.

An analytical expression for the output voltage of a single CMOS‐inverter/repeater driven long interconnects is developed. Delay analysis by the use of this expression, for long interconnects, modeled as RLC load, is compared with SPICE simulations. Good agreement between analytical and SPICE derived results is obtained.

The model works well for both sub‐micron and nanometer CMOS technologies. The maximum error in 90 percent fall time of output voltage is 7.5, 2.6 and 0.28 percent in 0.8 μm, 0.18 μm and 70 nm technologies, respectively. The maximum inaccuracy in case of high to low 50 percent propagation delay is about 5 percent for 0.8 μm, 3.1 percent for 0.18 μm and 2.3 percent in case of 70 nm technologies. The model shows a very good accuracy for nanometer technologies. The analysis shows that the use of scaled technologies along with voltage‐scaling leads to significant saving in power as well as delay improvement of a repeater driven long interconnect.

A new compact analytical expression for the output voltage of a single CMOS‐inverter driven long RLC interconnects is developed. The analysis carried out in the paper is of value to low‐power VLSI interconnect design.

This study aimed to identify the barriers and facilitators related to the implementation of radical innovations in secondary healthcare.

A systematic review was conducted and presented in accordance with a PRISMA flowchart. The databases PubMed and Web of Science were searched for original publications in English between the 1st of January 2010 and 6th of November 2020. The level of radicalness was determined based on five characteristics of radical innovations. The level of evidence was classified according to the level of evidence scale of the University of Oxford. The Consolidated Framework for Implementation Research was used as a framework to classify the barriers and facilitators.

Based on the inclusion and exclusion criteria, nine publications were included, concerning six technological, two organizational and one treatment innovation. The main barriers for radical innovation implementation in secondary healthcare were lack of human, material and financial resources, and lack of integration and organizational readiness. The main facilitators included a supportive culture, sufficient training, education and knowledge, and recognition of the expected added value.

To our knowledge, this is the first systematic review examining the barriers and facilitators of radical innovation implementation in secondary healthcare. To ease radical innovation implementation, alternative performance systems may be helpful, including the following prerequisites: (1) Money, (2) Added value, (3) Timely knowledge and integration, (4) Culture, and (5) Human resources (MATCH). This study highlights the need for more high-level evidence studies in this area.

The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.

Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.

For a driver interconnect load model terminated by an active gate load, a trade‐off exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such trade‐off does not exist. Many of the previous researches have modeled the active gate load at the terminating end by its input parasitic gate capacitance.

This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non‐optimal width selection, especially for large fan‐out conditions.

The finding is that the impedance matching between transmission line at driver and load ends plays an important role in estimation of overall power dissipation and transition delay of a VLSI circuit.

The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.

Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.

The simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.

This paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.

To analyze the effect of voltage scaling on crosstalk.

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. V_A (input at aggressor node A) and V_B (input at victim node B) switching in same direction; V_A is switching and V_B at static low; V_A and V_B are switching in opposite direction; V_A is switching and V_B at static high.

It is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.

Voltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.