Search results

1 – 6 of 6
To view the access options for this content please click here
Article
Publication date: 1 April 2000

Jarmo Määttänen, Petteri Palm and Aulis Tuominen

To achieve good reliability and high performance flip chip interconnection, process parameters and materials used in the flip chip process must be optimised. In this paper…

Abstract

To achieve good reliability and high performance flip chip interconnection, process parameters and materials used in the flip chip process must be optimised. In this paper reliability of Sn37Pb solder bumped flip chips on an FR5 board, using different fluxes and underfill materials, are tested in a temperature cycling test. Also the contact pad geometry used on the FR5 board had a great influence on the reliability of the joint. The solder bumps were grown on the well‐known TiW/Au under bump metallurgy (UBM1) with an extra layer of nickel (UBM2) which gives a reliable and high performance solder joint.

Details

Microelectronics International, vol. 17 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

To view the access options for this content please click here
Article
Publication date: 1 April 1999

Aulis Tuominen, Eero Ristolainen and Ville Lehtinen

Owing to the incessant demand for reductions in the size of portable electronics, new dense packaging technologies are required. Reflow soldering is still mainly used for…

Abstract

Owing to the incessant demand for reductions in the size of portable electronics, new dense packaging technologies are required. Reflow soldering is still mainly used for component joining on the substrate. In tiny joints such as those in flip chip (FC) assemblies the flux effect is vitally important and needs to pass a narrower performance window than in ordinary surface mount technology (SMT). The determination of the suitability of a flux, as reported in this paper, is twofold; first, the flux must perform well in its intended purpose and second, the flux must not leave harmful residues causing leakage or electromigration. The first test used was the wetting balance test for all fluxes. Fluxes accepted on the basis of the wetting tests were then subjected to the surface insulation resistance test (SIR).

Details

Soldering & Surface Mount Technology, vol. 11 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

To view the access options for this content please click here
Article
Publication date: 1 August 2004

Timo Liukkonen and Aulis Tuominen

Printed wiring board placement optimization of high‐speed placement machines in a high volume surface mount line was studied based on more careful analysis of the board…

Abstract

Printed wiring board placement optimization of high‐speed placement machines in a high volume surface mount line was studied based on more careful analysis of the board layout beforehand. In this method, the target is to get the board area to be assembled as small as possible in each successive placement machine, paying the most attention on component coordinates already during preliminary line balancing phase. Optimization and line balancing principles, that had showed promising results already in the first studies when compared to globally used well‐known commercial optimization systems, were now further developed. Results presented and illustrated in this paper show remarkable, comparable, improvement in both cycle time reduction and in balance of the whole surface mount line. The main difference between this method and the advanced commercial solutions is explained in detail. Board layout, feeder arrangement, sequence of fiducial registration, and XY‐table movement were taken into deeper consideration in the method.

Details

Microelectronics International, vol. 21 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

To view the access options for this content please click here
Article
Publication date: 1 April 2004

Timo Liukkonen, Pekka Nummenpää and Aulis Tuominen

The electronics industry will implement lead‐free soldering in the near future. Lead‐free implementation steps are divided into lead‐free process and lead‐free product…

Abstract

The electronics industry will implement lead‐free soldering in the near future. Lead‐free implementation steps are divided into lead‐free process and lead‐free product. The eutectic Sn/Ag/Cu alloy seems to have become the most widely used alloy in the implementation of lead‐free processes. In this study, the requirements for component placement are discussed from the lead‐free process point of view. Experiments concerning the self‐alignment capability and tack strength of both tin‐lead and lead‐free solder pastes are presented. According to the results, a bigger variation in self‐alignment capabilities can be expected when using a lead‐free paste. The paste properties affecting the self‐alignment mechanism and tack strength are also discussed.

Details

Soldering & Surface Mount Technology, vol. 16 no. 1
Type: Research Article
ISSN: 0954-0911

Keywords

To view the access options for this content please click here
Article
Publication date: 1 June 2002

Paavo Jalonen and Aulis Tuominen

Photolithographic techniques are universally employed in multi‐layer printed circuit board manufacturing. The growing demand for miniaturization of electronics means that…

Abstract

Photolithographic techniques are universally employed in multi‐layer printed circuit board manufacturing. The growing demand for miniaturization of electronics means that finer lines and smaller vias are increasingly required and these very fine lines on the substrate are increasingly difficult to produce by conventional means. One very promising means of meeting these fine line requirements is via the etching of sputtered thin films on a substrate and then growing copper on these lines using an additive method. In this work we tested the capability of an electrodeposited, positive‐acting photoresist for patterning thin film circuits on sputtered seed layers such as chromium. A fully additive electroless copper was then used to produce the copper lines. Epoxy reinforced fibreglass was used as a core material. The performance and quality properties of the process were examined, along with limitations of the process when compared with both a conventional dry film method and a spin coating method.

Details

Circuit World, vol. 28 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Content available
Article
Publication date: 1 December 1999

Abstract

Details

Microelectronics International, vol. 16 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

1 – 6 of 6