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Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit.

This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library.

Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA.

The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

The purpose of this paper is to illustrate the use of the p-median model to construct optimal patrol areas. This can improve both time spent traveling to calls, as well as equalize call load between patrol areas.

The paper provides an introduction to the use of integer linear programs to create optimal patrol areas, as many analysts and researchers in the author’s field will not be familiar with such models. The analysis then introduces a set of linear constraints to the p-median problem that are applicable to police agencies, such as constraining call loads to be equal and making patrol areas geographically contiguous.

The analysis illustrates the technique on simplified simulated examples. The analysis then demonstrates the utility of the technique by showing how patrol areas in Carrollton, TX can be made both more efficient and equalize the call loads given the same number of patrol beats as currently in place.

Unlike prior applications of creating patrol areas, this paper introduces linear constraints into the p-median problem, making it much easier to solve than programs that have non-linear or multiple objective functions. Supplementary code using open source software is also provided, allowing other analysts or researchers to apply the model to their own data.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

The objective of this study is to evaluate the overall technical efficiency, labor efficiency, capital efficiency and equipment efficiency of 30 Chinese construction sectors to foster sustainable economic growth in the construction industry.

This study employed the super-efficiency data envelopment analysis (SE-DEA) and artificial neural network model (ANN) to evaluate the industrial performance and improvement potential of the Chinese regional construction sectors from 2000 to 2017.

Results showed that the overall technical and capital efficiencies displayed relatively stable patterns. Equipment efficiency presented a relatively huge fluctuation during the sample period. Meanwhile, labor, capital and equipment efficiencies could potentially improve in the next five years. A spatial examination of efficiencies implied that the economic level was still a major factor in determining the efficiency performance of the regional construction industry. Beijing, Shanghai and Zhejiang were consistently the leading regions with the best performance in all efficiencies. Shandong and Hubei were critical regions with respect to their large reduction potential of labor, capital and equipment.

The study focused on the regional efficiency performance of the construction industry; however, it failed to further deeply discover the mechanism that captured the regional inefficiency. In addition, sample datasets used to predict might induce the accuracy of prediction results. Qualitative policy implications failed to regress the efficiency performance of the industrial policy variables. These limitations will be discussed in our further researches.

Enhancing the overall performance of the Chinese construction industry should focus on regions located in the western areas. In comparison with labor and capital efficiencies, equipment efficiency should be given priority by eliminating outdated equipment and developing high technology in the construction industry. In addition, the setting of the national reduction responsibility system should be stratified to account for regional variations.

The findings of this study can provide a systematic understanding for the current and future industry performance of the Chinese construction industry, which would help decision makers to customize appropriate strategies to improve the overall industrial performance with the consideration of regional differences.

The purpose of this paper is to evaluate the detection performance of infrared photoelectric detection system and establish stable tracking platform.

This paper puts forward making use of the finite element analysis method to set up the infrared radiation characteristics calculation model of flying target in infrared photoelectric detection system; researches the target optical characteristics based on the target imaging detection theory; sets up the heat balance equation of target’s surface node and gives the calculation method of total radiation intensity of flying target; and deduces the target detection distance calculation function; studies the changed regulation of radiation energy that charge coupled device (CCD) gain comes from target surface infrared heat radiations under different sky background luminance and different target flight attitude.

Through calculation and experiment analysis, the results show that when the target’s surface area increases or the target flight velocity is higher, the radiation energy that CCD obtained is higher, which is advantageous to the target stable detection in infrared photoelectric detection system.

This paper uses the finite element analysis method to set up the infrared radiation characteristics calculation model of flying target and give the calculation and experiment results; those results can provide some data and improve the design method of infrared photoelectric detection system, and it is of value.

In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.

The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.

A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.

This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

The purpose of this work in designing a wideband ring voltage-controlled oscillator (VCO) based on programmable current topology. It occupies a very tiny area yet achieving a good phase noise performance, which is suitable to be implemented in cost-effective and wideband frequency synthesizers.

The tuning range and gain are improved by dividing the VCO tuning curve into multiple curves controlled by programmable current sources without introducing additional parasitic capacitance.

Fabricated in 130-nm standard complementary metal oxide semiconductor technology and occupying an area of 0.079 mm², the VCO is tunable from 2.05 to 4.19 GHz, with a tuning percentage of 68.5 per cent. The VCO measures a phase noise performance of −96.7 dBc/Hz at an offset of 1 MHz from a 4.19 GHz carrier while consuming an average current of 6.5 mA, achieving figure of merit (FoM) and FoM_T of −158.9 and −175.6 dBc/Hz, respectively.

The proposed design uses programmable current topology without introducing parasitic capacitance, hence achieving wideband operation. It also occupies a tiny area and achieves a good phase noise performance.

Critical links in traffic networks are those who should be better protected because their removal has a significant impact on the whole network. So, the purpose of this paper is to identify the critical links of traffic networks.

This paper proposes the definition of the critical link for an urban traffic network and establishes mathematical model for determining critical link considering the travellers’ heterogeneous risk-taking behavior. Moreover, in order to improve the computational efficiency, the impact area of a link is quantified, a partial network scan algorithm for identifying the critical link based on the impact area is put forward and the efficient paths-based assignment algorithm is adopted.

The proposed algorithm can significantly reduce the search space for determining the most critical links in traffic network. Numerical results also demonstrate that the structure of efficient paths has significant impact on identifying the critical links.

This paper identifies the critical links by using a bi-level programming approach and proposes a partial network scan algorithm for identifying critical links accounting for travellers’ heterogeneous risk-taking behavior.

The nature and extent of our knowledge of stock market efficiency are examined. The development of “efficiency”, as a way of thinking about stock markets, is traced from Roberts (1959) and Fama (1965) onward. The early work successfully introduced competitive economic theory to the study of stock markets and paved the way for a flood of empirical research on the relation between information and stock prices. This literature irreversibly altered our views on stock market behavior. The theory and evidence of seemingly‐rational use of information lay in sharp contrast to prior beliefs. It was associated with a widespread increase in respect for stock markets, financial markets, and markets in general, at the time. Researchers began developing and using a variety of formal models of security prices. Nevertheless, “efficiency” has its limitations, both theoretically (as a way of characterizing markets) and empirically (by stretching the quality of the data, the estimation techniques used, and our knowledge of price behavior in competitive markets). Extensive evidence of anomalies suggests either that the market systematically misprices securities or that the theoretical or empirical limitations are binding, or both. The less interesting research question now is whether markets are efficient, and the more interesting question is how we can learn more about price and transactions behavior in competitive stock markets. The concept of an “efficient stock market” has stimulated both insight and controversy since Fama (1965) introduced it to the financial economics literature. As a construct, “efficiency” models the stock market in terms of the reaction of prices to the flow of information. Like all theory choices, modelling the market in this fashion involved tradeoffs. The benefits included opening the literature to an abundance of high‐quality researchable data, covering a variety of information, and the resulting insights obtained on the role of information in setting prices. The opportunity costs included temporarily closing the literature to alternative ways of viewing stock markets, for example by modelling public information as a homogenous good and thus ignoring factors such as differences in beliefs among investors, differences in information processing costs, and the “animal spirits” that might drive group behavior. The costs also included reliance on particular asset‐pricing models of how an “efficient” market would set prices. Not surprisingly, the ensuing deluge of research has produced some startling evidence, for and against the proposition that financial markets are “efficient”. Strongly‐conflicting views and puzzling anomalies remain. The early evidence seemed unexpectedly consistent with the theory. The theory, and its implications, also seemed clear at the time. After a period that seems short in retrospect, the growing body of evidence in favor of the efficient market hypothesis emerged as one of the most influential empirical areas of economics. Fama's (1970) review described a flourishing, coherent and confident literature. This research had an irreversible effect on our knowledge of and attitude toward stock markets, and financial markets generally. It coincided with an emergence of interest in, and respect for, all markets among economists and politicians, and influenced the worldwide trend toward “liberalizing” financial and other markets. The research consistently appeared to show an unbiased reaction of stock prices to public information. The property of “unbiased reaction” to public information, which formed the basis of the early definitions of “efficiency”, was seen to be an implication of rational, maximizing investor behavior in competitive securities markets (Fama 1965, p.4). Reduced to a basic level, the reasoning was that any systematicallybiased reaction to public information is costlessly publicly observable, and thus provides pure profit opportunities to be competed away. Characterizing the market in terms of its reaction to information is only one of many feasible ways of modelling stock price behavior, but it introduced economic theoryto the empirical studyof stock prices, which had received little serious attention from economists prior to that point. Despite the subsequent spate of anomalies, the early efficiency literature not only adapted standard economic theoryto provide the first formal economic insights into how stock prices behave, but it helped pave the way for an outporing of theoretical and empirical work on stock markets and capital markets in general. Subsequent empirical research was not as consistent with the theory. Evidence of “anomalous” return behavior now is widespread and well‐known. It generallytakes the form of variables (for example, size, day‐of‐the‐week, P/E ratio, market/book value ratio, rank of scaled earnings change, dividend yield) that are significantly but inexplicablyrelated to subsequent abnormal stock returns. Much of this evidence has defied rational economic explanation to date and appears to have caused many researchers to strongly qualify their views on market efficiency. Disagreement has not been not confined to the evidence. The literature has produced a variety of research designs, ranging from the “market model” of Fama, Fisher, Jensen and Roll (FFJR, 1969) to Shiller's (1981a,b) variance‐bounds tests. The very term “efficiency” has engendered controversy: there is a modest literature on precisely what efficiency means, on the role of transaction costs, and on whether efficient markets are logically feasible. Making sense of this literature requires careful definition of “efficiency” in this context and careful analysis of the type of evidence that has been offered in relation to it. This involves an assessment of the strengths and weaknesses of both the theory of efficient markets, as a way of characterizing stock markets, and of the data and research designs used in testing it. Not surprisingly, a mixed conclusion emerges. While the concept of efficient markets was an audacious departure from the comparative ignorance and suspicion among economists of stock markets that preceded it, and provides valuable insights into their behavior, the concept has its limitations, in terms of both its internal logical coherence and its fit with the data. Section 1 ofthis survey sketches the development of the efficient market theory, reviewing the principal contributions in terms of their usefulness in guiding and evaluating empirical research. Section 2 addresses the limitations inherent in what is knowable about stock market efficiency, given the present state of theory about how security prices might behave in an “efficient” market. It argues that there are binding limitations in the theoryof asset pricing, some of which are known and others of which are unknown or even unknowable. These limitations must be borne in mind when choosing whether to interpret the data as evidence of: (1) market efficiency, under the maintained hypothesis that a specific research design, including a specific model of asset pricing used to benchmark price behavior, correctly describes pricing in an efficient market; or (2) the ability of our models and research designs to encapsulate how prices behave in an efficient market, under the maintained hypothesis of efficiency. Against this background, section 3 then provides an assessment of the accomplishments of the theory of stock market efficiency, including an interpretation of the evidence. It focuses on the nature and influence of the evidence and does not attempt to provide a comprehensive literature taxonomy. The final section offers conclusions. The principal conclusion is that the theory of efficient markets has irreversibly enhanced our knowledge of and respect for stock markets (and perhaps for all financial market or even for markets in general) but that, like all theories, it is fundamentally flawed.

Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control.

All the modules used to design a RAM cell are designed using multilayer approach in QCA framework.

The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation.

Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures.

The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.