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This paper aims to investigate the effect of physical vapor deposition (PVD)-coated stencil wall aperture on the life span of fine-pitch stencil printing.

The fine-pitch stencil used in this work is fabricated by electroform process and subsequently nano-coated using the PVD process. Stencil printing process was then performed to print the solder paste onto the printed circuit board (PCB) pad. The solder paste release was observed by solder paste inspection (SPI) and analyzed qualitatively and quantitatively. The printing cycle of up to 80,000 cycles was used to investigate the life span of stencil printing.

The finding shows that the performance of stencil printing in terms of solder printing quality is highly dependent on the surface roughness of the stencil aperture. PVD-coated stencil aperture can prolong the life span of stencil printing with an acceptable performance rate of about 60%.

Stencil printing is one of the important processes in surface mount technology to apply solder paste on the PCB. The stencil’s life span greatly depends on the type of solder paste, stencil printing cycles involved and stencil conditions such as the shape of the aperture, size and thickness of the stencil. This study will provide valuable insight into the relationship between the coated stencil wall aperture via PVD process on the life span of fine-pitch stencil printing.

Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues.

In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types.

Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5.

Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.

The study investigates the sub process behaviour in stencil printing of type‐6 and type‐7 particle size distribution (PSD) Pb‐free solder pastes to assess their printing limits.

Two solder pastes were used in a design of experiments approach to find optimal printing parameters

Solder paste printing has been achieved to ultimately produce 30 μm deposits at 60 μm pitch for full area array patterns using a type‐7 Pb‐free solder paste. For a type‐6 PSD solder paste, full area array printing was limited to 50 μm deposits at 110 μm pitch. However, for peripheral printing patterns, 50 μm deposits at 90 μm pitch were obtained. The disparities in the behaviour of the two paste types at different geometries can be attributed to differences in the sub‐processes of the stencil printing. The paste release of the type‐6 paste from the stencil apertures at fine pitch was superior to the type‐7 paste, which may be attributed to the finer particle paste producing an increased drag force along the stencil aperture walls. However, the type‐7 paste was able to fill the smallest aperture openings, ultimately to 30 μm, thus producing full array printing patterns at uniquely small pitches.

This advancement in the stencil printing process has been made possible by refinements to both solder paste design and stencil manufacturing technology. Adjustments in the solder paste rheology have enabled successful printing at ultra fine pitch geometries. This, together with selecting appropriate printing parameters such as printing speed, pressure, print gap and separation speed, allows a practical printing process window. Moreover, advancements in stencil fabrication methods have produced “state‐of‐the‐art” stencils exhibiting very precisely defined aperture shapes, with smooth walls at very fine pitch, thus allowing for improved solder paste release at very small dimensions.

The results can be used to present a low cost solution for Pb‐free flip chip wafer bumping. Furthermore, the results indicate that type‐6 and type‐7 solder pastes should be applied to/selected for specific application geometries.

The purpose of this study is to quantify the relationship between the fluid flow and pressure drop for perforated plates. The homogenization of non-uniform fluid flows is often accomplished by passing the fluid through perforated plates. The underlying principle for the accomplishment of flow homogenization is a tradeoff of pressure drop for flow uniformity.

The investigation, implemented by numerical simulation, is based on turbulent flow in pipes and across perforated plates. The approach is as follows: (a) to devise a model to determine pressure drop’s fluid flow information from a single-aperture, (b) to obtain this information for apertures of different shapes, (c) to determine this type of information for perforated plates situated in a circular pipe, (d) to compare the entire perforated-plate pressure drop with that for a single-aperture modular and (e) to analyze two identical perforated plates in series.

The pressure drop results for the single-aperture modular model agreed very well with those for a whole perforated plate in a round pipe, therefore negating the need to simulate the more complex situation. In addition to the parametric study with aperture shape and Reynolds number, porosities (20-60 per cent) and plate thicknesses were also varied. The results obtained here compared favorably with experimental data.

This work demonstrates an efficient method for analyzing and obtaining useful pressure drop information for perforated plates. For the first time, the porous media approach for modeling perforated plates is compared directly to complete, full-scale perforated plate applications and identical plates in series.

Reflow solder joint quality is significantly affected by the ability of the solder to perfectly fill pad space and retain good solder joint shape. This study aims to investigate solder joint quality by quantitatively analyzing the stencil printing-deposited solder volume, solder height and solder coverage area.

The dispensability of different solder paste types on printed circuit board (PCB) pads using different stencil aperture shapes was evaluated. Lead-free Type 4 (20–38 µm particle size) and Type 5 (15–25 µm particle size) solder pastes were used to create solder joints according to standard reflow soldering.

The results show that the stencil aperture shape greatly affects the solder joint quality as compared with the type of solder paste. These investigations allow the development of new strategies for solving solder paste stencil printing issues and evaluating the quality of solder joints.

The reflow soldering process requires the appropriate selection of the stencil aperture shape according to the PCB and the solder paste according to the particle-size distribution of the solder alloy powder. However, there are scarce studies on the effects of stencil aperture shape and the solder alloy particle size on the solder paste space-filling ability.

The paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on the printing performance. As the current product miniaturisation trend continues, area array type package solutions are now being designed into products. The assembly of these devices requires the printing of very small solder paste deposits. The printing of solder pastes through small stencil apertures typically results in stencil clogging and incomplete transfer of paste to the PCB pads. At the very narrow aperture sizes required for flip‐chip applications, the paste rheology becomes crucial for consistent paste withdrawal. This is because, for smaller paste volumes, surface tension effects become dominant over viscous flow. Proper understanding of the effect of the key material, equipment and process parameters, and their interactions, is crucial for achieving high print yields. During the aperture filling and emptying sub‐process, the solder paste experiences forces/stresses as it interacts with the stencil aperture walls and the pad surfaces, which directly impact the paste flow within the apertures. As the substrate and stencil separate, the frictional/adhesive force on the stencil walls competes directly with the adhesives/pull force on the PCB pads, often resulting in incomplete paste transfer or skipping/clogged apertures. In this paper, we investigate the effect of stencil design on the printing process and in particular the effect on paste transfer efficiency.

The purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.

During the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.

The results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.

Due to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.

The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.

This paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.

This article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.

Stencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and therefore such a review paper should be of interest to a large selection of the electronics interconnect and assembly community.

Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.

Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.

Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.

Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

This paper describes the methodology used to evaluate several different stencil fabrication methods, aperture sizes and thicknesses and different solder pastes. Data collected included the number of printing defects and measurement of solder paste volume and height. Statistics have been used for the analysis of quantitative data. Results from this evaluation have been critical in the success of a new process for CSP assembly in a standard SMT environment. Stencil designs and solder paste selection for other applications have also benefited from the conclusions of this study.