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The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization – multi‐objective genetic algorithm (DLO‐MOGA) optimization scheme for system‐level synthesis.

The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence.

This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor‐level models for simulation of critical system‐level sub‐blocks. Consequently, for system‐level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog‐to‐digital converters on a 0.35 μm process.

The use of a hybrid DLO‐MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy.