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This paper aims to present an effective approach to integrated circuit (IC) throughput enhancement, called TΔT thermal control. It does not require any micro-architectural change of the IC. The only modification is the attachment of an additional temperature sensor at the heatsink boundary. TΔT control technique enables assessment of changes in the dimension of cooling conditions and quick reaction to the dynamic changes in the surrounding environment. As a result, the chip can operate flexibly while minimizing thermal violation.

Using additional knowledge about the surroundings, the on-chip temperature is regulated. The approach is first investigated theoretically. To validate the utilized thermal model, the measured temperature values of the designed and fabricated testing device are compared with the simulated one. The authors evaluated the impact of the additional sensor location on the reaction time (RT). Using the Spice model, further investigation helps to verify the hypothesis.

The control technique described in this paper showed that the temperature of the chip can be regulated using an additional knowledge of the surrounding environment. It has also been demonstrated that the attachment of an additional temperature sensor close to the cooled surface of the package enables TΔT thermal control technique to react faster (rapid powering up/down of the IC). Therefore, this lowers the risk of shutdown while keeping the temperature close to the thermal limit (the maximal temperature of the chip) for a significant period. The simulation results showed that a higher ambient temperature leads to diminution of the interval in which the on-chip temperature stays almost constant when TΔT technique is used (time shift).

In this study, a new thermal throttling technique that uses the full physical ability of the chip operating under thermal constraint has been evaluated.

The main goal of the work is to show how the kind of substrate and heat sink of integrated circuit or system influences the thermal dynamics of the circuit or system. The investigation leads to the solution of an unsteady state thermal model with analytic method and determination of the thermal time constants of various active and passive substrates and heat sinks. The results show that cheaper materials without any losses of thermal dynamics can replace expensive substrates and heat sinks. Theoretical procedure carried out step by step presents the way of unsteady state temperature computation with analytic method. It can be helpful for determination of the temperature of the chip during unsteady state in any point of the chip, average temperature and thermal time constant of the substrate.

This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS).

Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology.

Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption.

This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.

The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement.

Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run‐time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented.

The Hopfield network and parallel placement give comparable placements with the method using a simulated annealing algorithm. The parallel placement enables a decrease in total number of neurons and neuron connections which are necessary for simultaneous placement of all cells in a circuit.

This work provides a starting‐point for further research under hardware realization of the cell placement by using the Hopfield network. The presented solutions can be used for FPGA, gate array, sea‐of‐gates circuits and standard cell circuits with the same size cells.

The Hopfield network is used for placement in real circuits, in which nets contain multiple terminals, and for processing units in a parallel placement.

This paper aims present a thermal touch screen for the blind – a thermal tablet. A blind person using the device can imagine simple graphics or characters by touching flat thermal screen, which consists of reversible heat points, either warm or cold in different time. For the purpose, a thermal touch screen has been designed, fabricated and tested with a help of the blind.

The screen contains 294 Peltier modules working as reversible small heat sources that keep pre-set different temperature. The tablet can easily present thermal images and characters generated directly by an interfaced PC. Design methodology is based on own authors’ patent.

This paper presents original design and construction stages, as well as tests and usefulness of the device. The tests were carried out with participation of blind students who suggested how to tune the final parameters of the device in such a way that presentation and recognition of thermal information is easy and quick.

The thermal tablet consists of original hardware and software. Both of them collaborate each other and make the tablet useful for the blind. It has been proved by series of tests.

The paper aims to present the prototype of a graphical touch screen of thermal signs for the blind.

The surface of every Peltier pump is a touch point that demands the thermal stabilization. Miniature Peltier modules can work both as heat and cold generators. They are also able to measure the required dot temperature. Graphical screen of thermal signs displays a simple symbol or Brail text. Special computer program was made to control this innovative device. The software enables monitoring the temperature of each Peltier module.

The experiments carried out with blind people show that they are able to recognize hot and cold dots. Infrared photos of the device have been made using the thermographic MK525 camera.

The paper illustrates that it is possible to display simple graphics by using Peltier micropumps.

Examines the sixteenth published year of the ITCRR. Runs the whole gamut of textile innovation, research and testing, some of which investigates hitherto untouched aspects. Subjects discussed include cotton fabric processing, asbestos substitutes, textile adjuncts to cardiovascular surgery, wet textile processes, hand evaluation, nanotechnology, thermoplastic composites, robotic ironing, protective clothing (agricultural and industrial), ecological aspects of fibre properties – to name but a few! There would appear to be no limit to the future potential for textile applications.