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This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor.

The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established.

After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation.

An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.

This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.

The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.

Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.

Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.

BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.

FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

With the development of integrated circuit and communication technology, digital secure communication has become a research hotspot. This paper aims to design a five-dimensional fractional-order chaotic secure communication circuit with sliding mode synchronous based on microcontroller (MCU).

First, a five-dimensional fractional-order chaotic system for encryption is constructed. The approximate numerical solution of fractional-order chaotic system is calculated by Adomian decomposition method, and the phase diagram is obtained. Then, combined with the complexity and 0–1 test algorithm, the parameters of fractional-order chaotic system for encryption are selected. In addition, a sliding mode controller based on the new reaching law is constructed, and its stability is proved. The chaotic system can be synchronized in a short time by using sliding mode control synchronization.

The electronic circuit is implemented to verify the feasibility and effectiveness of the designed scheme.

It is feasible to realize fractional-order chaotic secure communication using MCU, and further reducing the synchronization error is the focus of future work.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

This paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.

In this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.

In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.

The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

The purpose of this paper is to construct a multiwing chaotic system that has hidden attractors with multiple stable equilibrium points. Because the multiwing hidden attractors chaotic systems are safer and have more dynamic behaviors, it is necessary to construct such a system to meet the needs of developing engineering.

By introducing a multilevel pulse function into a three-dimensional chaotic system with two stable node–foci equilibrium points, a hidden multiwing attractor with multiple stable equilibrium points can be generated. The switching behavior of a hidden four-wing attractor is studied by phase portraits and time series. The dynamical properties of the multiwing attractor are analyzed via the Poincaré map, Lyapunov exponent spectrum and bifurcation diagram. Furthermore, the hardware experiment of the proposed four-wing hidden attractors was carried out.

Not only unstable equilibrium points can produce multiwing attractors but stable node–foci equilibrium points can also produce multiwing attractors. And this system can obtain 2N + 2-wing attractors as the stage pulse of the multilevel pulse function is N. Moreover, the hardware experiment matches the simulation results well.

This paper constructs a new multiwing chaotic system by enlarging the number of stable node–foci equilibrium points. In addition, it is a nonautonomous system that is more suitable for practical projects. And the hardware experiment is also given in this article which has not been seen before. So, this paper promotes the development of hidden multiwing chaotic attractors in nonautonomous systems and makes sense for applications.

Detecting O₂ gas in a confined space at room temperature is particularly important to monitor the work process of precision equipment. This study aims to propose a miniaturized, low-cost, mass-scale produced O₂ sensor operating around 30°C.

The O₂ sensor based on lanthanum fluoride (LaF₃) solid electrolyte thin film was developed using MEMS technology. The principle of the sensor was a galvanic cell H₂O, O₂, Pt | LaF₃ | Sn, SnF₂ |, in which the Sn film was prepared by magnetron sputtering, and the LaF₃ film was prepared by thermal resistance evaporation.

Through pretreatments, the sensor’s response signal to 40% oxygen concentration was enhanced from 1.9 mV to 46.0 mV at 30°C and 97.0% RH. Tests at temperatures from 30°C to 50°C and humidity from 32.4% RH to 97.0% RH indicated that the output electromotive force (EMF) has a linear relationship with the logarithm of the oxygen concentration. The sensitivity of the sensor increases with an increase in both humidity and temperature in the couple mode, and the EMF of the sensor follows well with the Nernst equation at different temperatures and humidity.

This research could be applied to monitor the oxygen concentration below 25% in confined spaces at room temperature safely without a power supply.

The relationship between temperature and humidity coupling and the response of the sensor was obtained. The nano-film material was integrated with the MEMS process. It is expected to be practically applied in the future.

The hygroscopic properties of 3D-printed filaments and moisture absorption itself during the process result in dimensional inaccuracy, particularly for nozzle movement along the x-axis and for micro-scale features. In view of that, this study aims to analyze in depth the dimensional errors and deviations of the fused filament fabrication (FFF)/fused deposition modeling (FDM) 3D-printed micropillars (MPs) from the reference values. A detailed analysis into the variability in printed dimensions below 1 mm in width without any deformations in the printed shape of the designed features, for challenging filaments like polymethyl methacrylate (PMMA) has been done. The study also explores whether the printed shape retains the designed structure.

A reference model for MPs of width 800 µm and height 2,000 µm is selected to generate a g-code model after pre-processing of slicing and meshing parameters for 3D printing of micro-scale structure with defined boundaries. Three SETs, SET-A, SET-B and SET-C, for nozzle diameter of 0.2 mm, 0.25 mm and 0.3 mm, respectively, have been prepared. The SETs containing the MPs were fabricated with the spacing (S) of 2,000 µm, 3,200 µm and 4,000 µm along the print head x-axis. The MPs were measured by taking three consecutive measurements (top, bottom and middle) for the width and one for the height.

The prominent highlight of this study is the successful FFF/FDM 3D printing of thin features (<1mm) without any deformation. The mathematical analysis of the variance of the optical microscopy measurements concluded that printed dimensions for micropillar widths did not vary significantly, retaining more than 65% of the recording within the first standard deviation (SD) (±1 s). The minimum value of SD is obtained from the samples of SET-B, that is, 31.96 µm and 35.865 µm, for height and width, respectively. The %RE for SET-B samples is 5.09% for S = 2,000µm, 3.86% for S = 3,200µm and 1.09% for S = 4,000µm. The error percentage is so small that it could be easily compensated by redesigning.

The study does not cover other 3D printing techniques of additive manufacturing like stereolithography, digital light processing and material jetting.

The presented study can be potentially implemented for the rapid prototyping of microfluidics mixer, bioseparator and lab-on-chip devices, both for membrane-free bioseparation based on microfiltration, plasma extraction from whole blood, size-selection trapping of unwanted blood cells, and also for membrane-based plasma extraction that requires supporting microstructures. Our developed process may prove to be far more economical than the other existing techniques for such applications.

For the first time, this work presents a comprehensive analysis of the fabrication of micropillars using FDM/FFF 3D printing and PMMA in filament form. The primary focus of the study is to minimize the dimensional inaccuracies in the 3D printed devices containing thin features, especially in the area of biomedical engineering, by delivering benefits from the choice of the parameters. Thus, on the basis of errors and deviations, a thorough comparison of the three SETs of the fabricated micropillars has been done.

Multilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources.

A novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources.

The consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results.

The proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.