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The purpose of this paper is to define the process of analog circuit optimization on the basis of the control theory application. This approach produces many different strategies of optimization and determines the problem of searching of the best strategy in sense of minimal computer time. The determining of the best strategy of optimization and a searching of possible structure of this strategy with a minimal computer time is a principal aim of this work.

Different kinds of strategies for circuit optimization have been evaluated from the point of view of operations’ number. The generalized methodology for the optimization of analog circuit was formulated by means of the optimum control theory. The main equations for this methodology were elaborated. These equations include the special control functions that are introduced artificially. This approach generalizes the problem and generates an infinite number of different strategies of optimization. A problem of construction of the best algorithm of optimization is defined as a typical problem of the control theory. Numerical results show the possibility of application of this approach for optimization of electronic circuits and demonstrate the efficiency and perspective of the proposed methodology.

Examples show that the better optimization strategies that are appeared in limits of developed approach have a significant time gain with respect to the traditional strategy. The time gain increases when the size and the complexity of the optimized circuit are increasing. An additional acceleration effect was used to improve the properties of presented optimization process.

The obtained results show the perspectives of new approach for circuit optimization. A large set of various strategies of circuit optimization serves as a basis for searching the better strategies with a minimum computer time. The gain in processor time for the best strategy reaches till several thousands in comparison with traditional approach.

This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm.

The hybridization of whale optimization algorithm and modified gray wolf optimization (WOA-mGWO) algorithm is proposed, and the same is applied for the automated design of analog circuits.

The proposed hybrid WOA-mGWO algorithm demonstrates better performance in terms of convergence rates and average fitness of the function after testing it with 23 classical benchmark functions. Moreover, a rigorous performance evaluation is done with 20 independent runs using Wilcoxon rank-sum test.

For evaluating the performance of the proposed algorithm, a conventional two-stage operational amplifier is considered. The aspect ratios calculated by simulating the algorithm in MATLAB are later used to design the operational amplifier in Cadence environment using 180nm CMOS standard process.

The hybrid WOA-mGWO algorithm is tailored to improve the exploration ability of the algorithm by combining the abilities of two metaheristic algorithms, i.e. whale optimization algorithm and modified gray wolf optimization algorithm. To build further credence and to prove its profound existence in the latest state of the art, a statistical study is also conducted over 20 independent runs, for the robustness of the proposed algorithm, resulting in best, mean and worst solutions for analog IC sizing problem. A comparison of the best solution with other significant sizing tools proving the efficiency of hybrid WOA-mGWO algorithm is also provided. Montecarlo simulation and corner analysis are also performed to validate the endurance of the design.

In this paper, on the basis of a previously developed approach to circuit optimization, the main element of which is the control vector that changes the form of the basic equations, the structure of the control vector is determined, which minimizes CPU time.

The circuit optimization process is defined as a controlled dynamic system with a special control vector. This vector serves as the main tool for generalizing the problem of circuit optimization and produces a huge number of different optimization strategies. The task of finding the best optimization strategy that minimizes processor time can be formulated. There is a need to find the optimal structure of the control vector that minimizes processor time. A special function, which is a combination of the Lyapunov function of the optimization process and its time derivative, was proposed to predict the optimal structure of the control vector. The found optimal positions of the switching points of the control vector give a large gain in CPU time in comparison with the traditional approach.

The optimal positions of the switching points of the components of the control vector were calculated. They minimize processor time. Numerical results are obtained for various circuits.

The Lyapunov function, which is one of the main characteristics of any dynamic system, is used to determine the optimal structure of the control vector, which minimizes the time of the circuit optimization process.

This paper aims to propose a new approach on the problem of circuit optimisation by using the generalised optimisation methodology presented earlier. This approach is focused on the application of the maximum principle of Pontryagin for searching the best structure of a control vector providing the minimum central processing unit (CPU) time.

The process of circuit optimisation is defined mathematically as a controllable dynamical system with a control vector that changes the internal structure of the equations of the optimisation procedure. In this case, a well-known maximum principle of Pontryagin is the best theoretical approach for finding of the optimum structure of control vector. A practical approach for the realisation of the maximum principle is based on the analysis of the behaviour of a Hamiltonian for various strategies of optimisation and provides the possibility to find the optimum points of switching for the control vector.

It is shown that in spite of the fact that the maximum principle is not a sufficient condition for obtaining the global minimum for the non-linear problem, the decision can be obtained in the form of local minima. These local minima provide rather a low value of the CPU time. Numerical results were obtained for both a two-dimensional case and an N-dimensional case.

The possibility of the use of the maximum principle of Pontryagin to a problem of circuit optimisation is analysed systematically for the first time. The important result is the theoretical justification of formerly discovered effect of acceleration of the process of circuit optimisation.

In this paper, we propose further development of the generalized methodology for analogue circuit optimization. This methodology is based on optimal control theory. This approach generates many different circuit optimization strategies. We lead the problem of minimizing the CPU time needed for circuit optimization to the classical problem of minimizing a functional in optimal control theory.

The process of analogue circuit optimization is defined mathematically as a controllable dynamical system. In this context, we can formulate the problem of minimizing the CPU time as the minimization problem of a transitional process of a dynamical system. To analyse the properties of such a system, we propose to use the concept of the Lyapunov function of a dynamical system. This function allows us to analyse the stability of the optimization trajectories and to predict the CPU time for circuit optimization by analysing the characteristics of the initial part of the process.

We present numerical results that show that we can compare the CPU time for different circuit optimization strategies by analysing the behaviour of a special function. We establish that, for any optimization strategy, there is a correlation between the behaviour of this function and the CPU time that corresponds to that strategy.

The analysis shows that Lyapunov function of optimization process and its time derivative can be informative sources for searching a strategy, which has minimal processor time expense. This permits to predict the best optimization strategy by analyzing only initial part of the optimization process.

In this paper, the previously developed idea of generalized optimization of circuits for deterministic methods has been extended to genetic algorithm (GA) to demonstrate new possibilities for solving an optimization problem that enhance accuracy and significantly reduce computing time.

The disadvantages of GAs are premature convergence to local minima and an increase in the computer operation time when setting a sufficiently high accuracy for obtaining the minimum. The idea of generalized optimization of circuits, previously developed for the methods of deterministic optimization, is built into the GA and allows one to implement various optimization strategies based on GA. The shape of the fitness function, as well as the length and structure of the chromosomes, is determined by a control vector artificially introduced within the framework of generalized optimization. This study found that changing the control vector that determines the method for calculating the fitness function makes it possible to bypass local minima and find the global minimum with high accuracy and a significant reduction in central processing unit (CPU) time.

The structure of the control vector is found, which makes it possible to reduce the CPU time by several orders of magnitude and increase the accuracy of the optimization process compared with the traditional approach for GAs.

It was demonstrated that incorporating the idea of generalized optimization into the body of a stochastic optimization method leads to qualitatively new properties of the optimization process, increasing the accuracy and minimizing the CPU time.

The purpose of this paper is to demonstrate the application of river formation dynamics to size the widths of power distribution network for very large-scale integration designs so that the wire area required by power rails is minimized. The area minimization problem is transformed into a single objective optimization problem subject to various design constraints, such as IR drop and electromigration constraints.

The minimization process is carried out using river formation dynamics heuristic. The random probabilistic search strategy of river formation dynamics heuristic is used to advance through stringent design requirements to minimize the wire area of an over-designed power distribution network.

A number of experiments are performed on several power distribution benchmarks to demonstrate the effectiveness of river formation dynamics heuristic. It is observed that the river formation dynamics heuristic outperforms other standard optimization techniques in most cases, and a power distribution network having 16 million nodes is successfully designed for optimal wire area using river formation dynamics.

Although many research works are presented in the literature to minimize wire area of power distribution network, these research works convey little idea on optimizing very large-scale power distribution networks (i.e. networks having more than four million nodes) using an automated environment. The originality in this research is the illustration of an automated environment equipped with an efficient optimization technique based on random probabilistic movement of water drops in solving very large-scale power distribution networks without sacrificing accuracy and additional computational cost. Based on the computation of river formation dynamics, the knowledge of minimum area bounded by optimum IR drop value can be of significant advantage in reduction of routable space and in system performance improvement.

Lack of optimization and improvement on experimental circuits precludes comprehensive statements. It is a deficiency of the existing chaotic circuit technology. One of the aims of this paper is to solve the above mentioned problems. Another purpose of this paper is to construct a 10 + 4-type chaotic secure communication circuit based on the proposed third-order 4 + 2-type circuit which can output chaotic phase portraits with high accuracy and high stability.

In Section 2 of this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new third-order Lorenz-like chaotic system is proposed based on the 4 + 2 circuit. Then some simulations are presented to verify that the proposed system is chaotic by using Multisim software. In Section 3, a fourth-order chaotic circuit is proposed on the basis of the third-order 4 + 2 chaotic circuit. In Section 4, the circuit design method of this paper is applied to chaotic synchronization and secure communication. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. In Section 5, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented in an analog electronic circuit. The analog circuit implementation results match the Multisim results.

The simulation results show that the proposed fourth-order chaotic circuit can output six phase portraits, and it can output a stable fourth-order double-vortex chaotic signal. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. The scheme has the advantages of clear thinking, efficient and high practicability. The experimental results show that the precision is improved by 2-3 orders of magnitude. Signal-to-noise ratio meets the requirements of engineering design. It provides certain theoretical and technical bases for the realization of a large-scale integrated circuit with a memristor. The proposed circuit design method can also be used in other chaotic systems.

In this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new chaotic system is proposed on the basis of the 4 + 2 chaotic circuit for the first time. Some simulations are presented to verify its chaotic characteristics by Multisim. Then the novel third-order 4 + 2 chaotic circuit is applied to construct a fourth-order chaotic circuit. Simulation results verify the existence of the new fourth-order chaotic system. Moreover, a new 10 + 4-type chaotic secure communication circuit is proposed based on chaotic synchronization of the novel third-order 4 + 2 circuit. To illustrate the effectiveness of the proposed scheme, the intensity limit and stability of the transmitted signal, the characteristic of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. Finally, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented through an analog electronic circuit, which are characterized by their high accuracy and good robustness. The analog circuit implementation results match the Multisim results.

The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization – multi‐objective genetic algorithm (DLO‐MOGA) optimization scheme for system‐level synthesis.

The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence.

This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor‐level models for simulation of critical system‐level sub‐blocks. Consequently, for system‐level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog‐to‐digital converters on a 0.35 μm process.

The use of a hybrid DLO‐MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy.

The current challenge for forecasting smart meters electricity consumption lies in the uncertainty and volatility of load profiles. Moreover, forecasting the electricity consumption for all the meters requires an enormous amount of time. Most papers tend to avoid such complexity by forecasting the electricity consumption at an aggregated level. This paper aims to forecast the electricity consumption for all smart meters at an individual level. This paper, for the first time, takes into account the computational time for training and forecasting the electricity consumption of all the meters.

A novel hybrid autoregressive-statistical equations idea model with the help of clustering and whale optimization algorithm (ARSEI-WOA) is proposed in this paper to forecast the electricity consumption of all the meters with best performance in terms of computational time and prediction accuracy.

The proposed model was tested using realistic Irish smart meters energy data and its performance was compared with nine regression methods including: autoregressive integrated moving average, partial least squares regression, conditional inference tree, M5 rule-based model, k-nearest neighbor, multilayer perceptron, RandomForest, RPART and support vector regression. Results have proved that ARSEI-WOA is an efficient model that is able to achieve an accurate prediction with low computational time.

This paper presents a new hybrid ARSEI model to perform smart meters load forecasting at an individual level instead of an aggregated one. With the help of clustering technique, similar meters are grouped into a few clusters from which reduce the computational time of the training and forecasting process. In addition, WOA improves the prediction accuracy of each meter by finding an optimal factor between the average electricity consumption values of each cluster and the electricity consumption values for each one of its meters.