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The smart image sensor (SIS) which integrated with both sensor and smart processor has been widely applied in vision-based intelligent perception. In these applications, the linearity of the image sensor is crucial for better processing performance. However, the simple source-follower based readout circuit in the conventional SIS introduces significant nonlinearity. This paper aims to design a low-power in-pixel buffer circuit applied in the high-linearity SIS for the smart perception applications.

The linearity of the SIS is improved by eliminating the non-ideal effects of transistors and cancelling dynamic threshold voltage that changes with the process variation, voltage and temperature. A low parasitic capacitance low leakage switch is proposed to further improve the linearity of the buffer. Moreover, an area-efficient SIS architecture with a sharing mechanism is presented to further reduce the number of in-pixel transistors.

A low parasitic capacitance low leakage switch and a gate-source voltage pre-storage method are proposed to further improve the linearity of the buffer. Nonlinear effects introduced by parasitic capacitance switching leakage, etc., have been investigated and solved by proposing low-parasitic and low-leakage switches. The linearity is improved without a power-hungry operational amplifier-based calibration circuit and a noticeable power consumption increment.

The proposed design is implemented using a standard 0.18-µm CMOS process with the active area of 102 µm². At the power consumption of 5.6 µW, the measured linearity is −63 dB, which is nearly 27 dB better than conventional active pixel sensor (APS) implementation. The proposed low-power buffer circuit increase not only the performance of the SIS but also the lifetime of the smart perception system.

The Center for Industrial Research (SI), the University of Oslo (UiO) and a group of Norwegian companies have collaborated between 1990 and 1992 in the research programme ‘Industrial Microelectronics’ with a total cost of 30 MNOK. The programme was sponsored by the Norwegian Scientific and Industrial Research Council (NTNF) as one of the twin programmes constituting a national research initiative in microelectronics. The motivation for the programme is the recognition of microelectronics as a key technology commanding the performance and market success of many of the electronics systems from the Norwegian electronics industry towards the year 2000. The main objective is to stimulate industrial innovation by developing, transferring and exploiting knowledge and methods based upon advanced microelectronics. Focused activities are silicon sensor technology, combined analogue/digital design of application‐specific integrated circuits, large scale instrumentation, sensor packaging and thermal management of electronic systems. SI is focusing on applied research, UiO on education, and collaborating Norwegian companies are using the results in their own R&D projects. It is anticipated that the research results will be fully industrialised within 3–5 years. The programme is co‐ordinated with other Norwegian government‐sponsored research activities as well as European research programmes based on microelectronics. The programme is organised in projects and monitored with a set of milestones strongly indicating the achievement of successful industrial innovation, research results of international standing and high‐quality education of key personnel for the industry. Several successful examples of the research results are highlighted: Design and process methodology for double‐sided microstrip silicon radiation sensors for detection of high energy elementary particles, silicon‐to‐silicon and silicon‐to‐thin film anodic bonding processes for sensor fabrication, combined analogue/digital application‐specific integrated circuits for front‐end instrumentation applications, packaging of radiation sensors and thermal management of electronic systems by evaporation cooling. It is concluded that the programme has successfully achieved results in harmony with the objective.

This paper documents the development of a microcontroller‐based humidity sensing system. The humidity sensors are manufactured by thin film technology from a novel combination of SiO/In₂O₃. The fabrication and characterization of the sensor samples is presented and discussed in this paper. The sensor pattern consists of an interdigitated conductor on top of which the sensing layer is deposited. A humidity sensitivity of 0.25%/RH% and a thermal sensitivity of 0.103%/°C has been measured. The samples exhibit a low drift over a one‐year time span (0.0013RH%/yr), low hysteresis (0.34RH%), good linearity (±2RH%) and a reasonably fast time response (18 sec). The entire sensor system has been analyzed mathematically and the necessary algorithms for error‐compensation have been developed. The resulting measurement system is efficient, accurate and flexible.

Two major computerized systems, ECG and Clinical Chemistry, have been meshed on an 1BM‐1800/System/7 tandem combination. The System/7 computer serves as (1) an analog‐to‐digital device acquiring both ECG data from 3‐channel data acquisition carts over telephone lines, and laboratory data from autoanalyzers over direct cabling; and (2) a communications concentrator controlling a network of interactive video display units and printers in both the Clinical Chemistry and the ECG Laboratories via asynchronous and synchronous multiplexers. An operating system has been written for the System/7 which handles all I/O from external devices and communicates to the 1BM‐1800 over a direct memory access channel at the rate of 105 words per second. The meshing of the systems has a synergistic effect which makes the system extremely powerful at an economic price level.

The purpose of this paper is to propose a detailed analysis of a memristor-based differentiating circuit with buffering amplifier, a capacitor and a memristor.

The analyzed circuit is based on a resistor–capacitor differentiating scheme together with a buffering operational amplifier. In the proposed circuit, the resistor is replaced by a memristor element.

The considered circuit and its classical analog are investigated using a rectangular pulse sequence as input signal. A comparison between the derived results is made. An advantage of the proposed memristor circuit is the shortened duration, i.e. higher localization, of the output pulses of rectangular input pulses to be derived.

Differentiating circuits are important modules in radio-electronics. Because of their widespread usage, it is of higher interest that their new potential schematic realizations are analyzed. For the computer simulations, a previously proposed modified nonlinear memristor model is used. Several of the best and widely used basic memristor models are applied as well.

The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures.

The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V.

Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm² DAC consumed 12.6 mW for the data conversion.

This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

Due‐date performance (DDP) is a very important performance indicator for the companies. Thus, companies with a high hit rate would have greater competitive advantage; on the contrary, companies that delay customers' orders frequently would lose sales opportunities and reputations. Therefore, there were many academic studies and practical efforts to improve DDP in the past, but the problem of low hit rate still exists. In order to increase the hit rate, some companies have focused on reducing the variation, while others focus on production management, but is the real problem affecting the low rate variability or production management? This is indeed difficult to be validated through practice. Therefore, this study designed three scenarios, tested each scenario for 30 times, each test involved seven subjects. The tests were to provide counter‐evidence in the Job Shop environment without variation. If the variation is the main factor of affecting hit rate, the rate at this time should be good; otherwise, the assumption that variation is the main cause is rebutted. The results demonstrated that production management planning is the main cause, and the method of enhancing the hit rate is obtained during the test.