The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration…
The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). This paper presents an overview of the general problem of designing zero-aliasing or aliasing-free space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with extensive simulation results on International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and COMPACTEST.
Radio frequency identification (RFID) is a technology for tracking objects that is expected to be widely adopted in very near future. A reader device sends probes to a set…
Radio frequency identification (RFID) is a technology for tracking objects that is expected to be widely adopted in very near future. A reader device sends probes to a set of RFID tags, which then respond to the request. A tag is recognized only when it is the only one to respond to the probe. Only reader has collision detection capability. The problem considered here is to minimize the number of probes necessary for reading all the tags, assuming that the number of tags is known in advance.
Well known binary and n‐ary partitioning algorithms can be applied to solve the problem for the case of known number of tags. A new randomized hybrid tag identification protocol has been proposed, which combines the two partitioning algorithms into a more efficient one. The new scheme optimizes the binary partition protocol for small values of n (e.g. n=2, 3, 4). The hybrid scheme then applies n‐ary partition protocol on the whole set, followed by binary partition on the tags that caused collision.
It is analytically proved that the expected number of time slots in the hybrid algorithm with known number of users is less than 2.20 n. Performance of these algorithms was also evaluated experimentally, and an improvement from en to approximately 2.15 n was obtained.
The algorithm shown here is efficient both by theory and practice and outperforms existing ones.