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This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.

This paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.

The short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.

The dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.

The research results provide a reference for the design of protection system.

The key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

This study aims to extend the driving range by on-board charging with use of photovoltaic (PV) source, avoiding the dependency on the grid supply and energy storage system in addition to that reduce the conversion complexity influenced on converter section of electric vehicle (EV) system.

This paper proposed a PV fed integrated converter topology called integrated single-input multi-output (I-SIMO) converter with enriched error tolerant fuzzy logic controller (EET-FLC) based control technique to regulate the speed of brushless direct current motor drive. I-SIMO converter provides both direct current (DC) and alternating current (AC) outputs from a single DC input source depending on the operation mode. It comprises two modes of operation, act as DC–DC converter in vehicle standby mode and DC–AC converter in vehicles driving mode.

The use of PV panels in the vehicle helps to reduce dependence of grid supply as well as vehicle’s batteries. The proposed topology has to remove the multiple power conversion stages in EV system, reduce components count and provide dual outputs for enhancement of performance of EV system.

The proposed topology leads to reduction of switching losses and stresses across the components of the converter and provides reduction in system complexity and overall expenditure. So, it enhances the converter reliability and also improves the efficiency. The converter provides ripple-free output voltage under dynamic load condition. The performance of EET-FLC is studied by taking various performance measures such as rise time, peak time, settling time and peak overshoot and compared with conventional control designs.

This study aims to discover a practical and effective way to apply the quality cost concept in Strategic Cost Management (SCM) framework. The interaction of preventive, appraisal and failure (PAF) activities in a company's internal value chain will be the starting point of SCM implementation.

This study begins by establishing value chain and quality costs as the scope of conceptual analysis. Discussions on the interrelationships between activities, quality and costs were gathered to clarify conceptual and practical gaps in the scope of the study. The PAF quality cost model is applied to find viable, practical solutions. The costs of activities will serve as performance indicators.

The PAF quality cost model depicts opportunities to lower costs and increase profit in a business simultaneously; current poor quality costs are the benchmark. Identifying PAF activities and costs in the business value chain and linking it with others is crucial in evaluating SCM applications. These linkages will generate a Quality Cost Chain (QCC). The leading indicator of improvement is a higher ratio between new possible failure costs (FC) and the combination of prevention and appraisal costs (PAC) than the current value, followed by a lower total quality cost (TQC). The subsequent attention is a lower ratio between the appraisal cost (AC) and prevention cost (PC). Mathematically, for assessing the operability of new quality-related activities, ΔPAC_new < ΔFC_new, TQC_new < TQC_current, (FC/PC)_new>(FC/PC)_current and (AC/PC)_new<(AC/PC)_current are proposed as feasible conditional-quantitative improvement criteria.

This study only discusses the relationship between quality costs and activities related to quality management in the PAF quality cost model, not cost behavior. This limitation opens up opportunities for future research that intends to link QCC with cost behavior in the context of managerial accounting and Strategic Cost Management. The use of QCC in certain industrial areas is the next research opportunity. The variety of PAF activities this study addresses originates from a wide range of industrial sectors; QCC research by sector may produce unique industrial quality cost phenomena.

QCC will make it easier for managers to evaluate how strategically their departments or activities contribute to quality costs at the departmental or organizational level, as well as to effectively and efficiently improve quality cost performance.

The quality-related activity and quality cost issues are still rarely treated as subjects of research studies in the field of Strategic Cost Management. Even so, the discussion tends to be very broad, complex and difficult to apply. This study combines a simple diagrammatic and mathematical approach to simplify the discussion and, at the same time, manage the value of strategic quality management.

This paper aims to study a multi-level reinjection current source converter (MLR-CSC) that adds attracting properties such as the self-commutation and pulse multiplication to the thyristor converter, which is of great significance for increasing the device capacity and reducing current harmonics on the grid side. Particularly, designing advantageous driving methods of the reinjection circuit is a critical issue that impacts the harmonic reduction and operation reliability of the MLR-CSC.

To deal with the mentioned issue, this paper takes the five-level reinjection current source converter (FLR-CSC), which is a type of the MLR-CSC, as the research object. Then, a method that can fully use combinations of five-level reinjection switching functions based on the concept of decomposition and recombination is proposed. It is worthy to mention that the proposed method can be easily extended to other multi-level reinjection circuits. Moreover, the working principle of the three-phase bridge circuit based on semi-controlled thyristors in the FLR-CSC that can achieve the four-quadrant power conversion is analyzed in detail.

Finally, the simulation and experimental results of FLR-CSC verify the effectiveness of the proposed reinjection circuit driving method and the operating principle of four-quadrant power conversion in this paper.

The outstanding features of the proposed driving method for FLR-CSC in this paper include combinations of reinjection switching functions that are fully exploited through three simple steps and can be conveniently extended to other multi-level reinjection circuits.

This paper aims to introduce a new fault protection scheme for microgrid DC networks with ring buses.

It is well recognized that the protection scheme in a DC ring bus microgrid becomes very complicated due to the bidirectional power flow. To provide reliable protection, the differential current signal is decomposed into several basic modes using adaptive variational mode decomposition (VMD). In this method, the mode number and the penalty factor are chosen optimally by using arithmetic optimization algorithm, yielding satisfactory decomposition results than the conventional VMD. Weighted Kurtosis index is used as the measurement index to select the sensitive mode, which is used to evaluate the discrete Teager energy (DTE) that indicates the occurrence of DC faults. For localizing cable faults, the current signals from the two ends are used on a sample-to-sample basis to formulate the state space matrix, which is solved by using generalized least squares approach. The proposed protection method is validated in MATLAB/SIMULINK by considering various test cases.

DTE is used to detect pole-pole and pole-ground fault and other disturbances such as high-impedance faults and series arc faults with a reduced detection time (10 ms) compared to some existing techniques.

Verification of this method is performed considering various test cases in MATLAB/SIMULINK platform yielding fast detection timings and accurate fault location.

Multilevel inverters play a major role in the development of high-power industrial applications. In traditional low-level inverters (e.g. 2-level), the switching frequency is restricted and the harmonic spectrum of the system is hard to meet power requirements. Similarly, high-level inverters consist of a large number of switches, complex modulation techniques and complex hardware architecture, which results in high power loss and a significant amount of harmonic distortion. Furthermore, it is a must to ensure that every switch experiences the same stress of voltage and current. The purpose of this paper is to present an inverter topology with lower conduction and switching losses via reduced number of switches and equal voltage source-sharing technique.

Herein, the authors present a cascaded multilevel inverter having less power switches, a simple modulation technique and an equal voltage source-sharing phenomenon implementation.

The modulation technique becomes more complex when equal voltage source-sharing is to be implemented. In this study, a novel topology for the multilevel inverter with fewer switches, novel modulation technique, equal voltage source-sharing and Inductor-Capacitor-Inductor filter implementation is demonstrated to the reduce harmonic spectrum and power losses of the proposed system.

The nine-level inverter design is validated using software simulations and hardware prototype testing; the power losses of the proposed inverter design are elaborated and compared with the traditional approach.

This study aims to design and validate a theoretical model for capacitive imaging (CI) sensors that incorporates the interelectrode shielding and surrounding shielding electrodes. Through experimental verification, the effectiveness of the theoretical model in evaluating CI sensors equipped with shielding electrodes has been demonstrated.

The study begins by incorporating the interelectrode shielding and surrounding shielding electrodes of CI sensors into the theoretical model. A method for deriving the semianalytical model is proposed, using the renormalization group method and physical model. Based on random geometric parameters of CI sensors, capacitance values are calculated using both simulation models and theoretical models. Three different types of CI sensors with varying geometric parameters are designed and manufactured for experimental testing.

The study’s results indicate that the errors of the semianalytical model for the CI sensor are predominantly below 5%, with all errors falling below 10%. This suggests that the semianalytical model, derived using the renormalization group method, effectively evaluates CI sensors equipped with shielding electrodes. The experimental results demonstrate the efficacy of the theoretical model in accurately predicting the capacitance values of the CI sensors.

The theoretical model of CI sensors is described by incorporating the interelectrode shielding and surrounding shielding electrodes into the model. This comprehensive approach allows for a more accurate evaluation of the detecting capability of CI sensors, as well as optimization of their performance.

Additive manufacturing (AM) can achieve significant weight savings with only minor compromises in strength if high-performance wrought aluminum alloys are used as feedstock. Despite the advantages in strength that aluminum alloys (AA) 6061 offer, they cannot be manufactured via printing because of hot cracking and other solidification problems. The purpose of this study is to achieve high-quality printing of AA6061 with nanotreated wires.

Nanotreating was used to modify the AA6061 alloy composition by adding a small fraction of nanoparticles to enhance the alloy’s manufacturability and resultant properties. Wire arc additive manufacturing (WAAM) was used to print the nanotreated AA6061 wire feedstock. The microstructure of the printed AA6061 was characterized by X-ray crystallography, optical microscopy, scanning electron microscopy and energy dispersive spectroscopy mapping. The microhardness profile, tensile behavior and fracture surface were analyzed.

This work successfully used WAAM to print nanotreated AA 6061 components. The resulting AA6061 parts were crack-free, with exceptional grain morphology and superior mechanical properties. Owing to the excellent size control capabilities of nanoparticles, a homogeneous distribution of small grains was maintained in all deposited layers, even during repeated thermal cycles.

Previous studies have not successfully printed AA6061 using WAAM. Conventional WAAM products exhibit anisotropic mechanical properties. The nanotreated AA6061 was successfully printed to achieve homogeneous microhardness and isotropic tensile properties. The promising results of this study reflect the great potential of nanotech metallurgy as applied to the WAAM process.

Dielectric barrier discharge (DBD) is widely used in the treatment of skin disease, surface modification of material and other fields of electronics. The purpose of this paper is to design a high-performance power supply with a compact structure for excimer lamps in electronics application.

To design a high-performance power supply with a compact structure remains a challenge for excimer lamps in electronics application, a current-source type power supply in a single stage with power factor correction (PFC) is proposed. It consists of an excitation voltage generation unit and a PFC unit. By planning the modes of the excitation voltage generation unit, a bipolar pulse excitation voltage with a high rising and falling rate is generated. And a high power factor (PF) on the AC side is achieved by the interaction of a non-controlled rectifier and two inductors.

The experimental results show that not only a high-frequency and high-voltage bipolar pulse excitation voltage with a high average rising and falling rate (7.51GV/s) is generated, but also a high PF (0.992) and a low total harmonic distortion (5.54%) is obtained. Besides, the soft-switching of all power switches is realized. Compared with the sinusoidal excitation power supply and the current-source power supply, the proposed power supply in this paper can take advantage of the potential of excimer lamps.

A new high-performance power supply with a compact structure for DBD type excimer lamps is proposed. The proposed power supply can work stably in a wide range of frequencies, and the smooth regulation of the discharge power of the excimer lamp can be achieved by changing the switching frequency. The ideal excitation can be generated, and the soft switching can be realized. These features make this power supply a key player in the outstanding performance of the DBD excimer lamps application.

The purpose of this paper is to investigate the applicability of a direct current (DC) hysteresis measurement on power transformer terminals for the subsequent hysteresis model parametrization in transformer grey box topology models.

Two transformer topology models with two different hysteresis models are used together with a DC hysteresis measurement via the power transformer terminals to parameterize the hysteresis models by means of an optimization. The calculated current waveform with the derived model in the transformer no-load condition is compared to the measured no-load current waveforms to validate the model.

The proposed DC hysteresis measurement via the power transformer terminals is suitable to parametrize two hysteresis models implemented in transformer topology models to calculate the no-load current waveforms.

Different approaches for the measurement and utilization of transformer terminal measurements for the hysteresis model parametrization are discussed in literature. The transformer topology models, derived with the presented approach, are able to reproduce the transformer no-load current waveform with acceptable accuracy.