Hitachi achieves 40 per cent reduction in PCB place-and-route design time with cadence global route environment

Citation

(2010), "Hitachi achieves 40 per cent reduction in PCB place-and-route design time with cadence global route environment", Soldering & Surface Mount Technology, Vol. 22 No. 1. https://doi.org/10.1108/ssmt.2010.21922aab.003

Hitachi achieves 40 per cent reduction in PCB place-and-route design time with cadence global route environment

Article Type: Industry news From: Soldering & Surface Mount Technology, Volume 22, Issue 1

The Cadence^® Global Route Environment (GRE) technology for Cadence Allegro^® printed circuit board (PCB) design enabled Hitachi, Ltd to successfully reduce PCB place-and-route design time by 40 per cent for a high-speed communication product. Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available. The time-saving results were reported by Hitachi Communication Technologies, Ltd, the communication products division of Hitachi Group, as part of a companywide initiative at Hitachi to enhance design efficiency and reduce design-cycle time.

The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCB, and establishes a new PCB design paradigm. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process, it allows users to plan the routing strategy at a high-level through interconnect flow designer. Through the interconnect feasibility capability, it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints. In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach becomes very effective for memory interfaces such as DDR2, DDR3 and serial interfaces such as PCI express and PCI express Gen II with their stringent high-speed design constraints.

At Hitachi, automatic routing had not previously been available to route signals with high-speed constraints. The GRE technology dramatically improves the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths. With GRE, Hitachi was able to effectively manage PCB designs with various trade-offs. Hitachi expects further reduction of design time as the GRE performance and features are updated and further enhanced.

In March 2007, Hitachi and Cadence jointly announced that Hitachi had standardized on Cadence EDA products in order to enhance design efficiency and reduce the design-cycle time for Hitachi’s hardware products as part of its focus on the company’s manufacturing capability.