The 7th VLSI Packaging Workshop of Japan 30 November-2 December 2004

Soldering & Surface Mount Technology

ISSN: 0954-0911

Article publication date: 1 April 2004

179

Citation

(2004), "The 7th VLSI Packaging Workshop of Japan 30 November-2 December 2004", Soldering & Surface Mount Technology, Vol. 16 No. 1. https://doi.org/10.1108/ssmt.2004.21916aaa.003

Publisher

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Emerald Group Publishing Limited

Copyright © 2004, Emerald Group Publishing Limited


The 7th VLSI Packaging Workshop of Japan 30 November-2 December 2004

The 7th VLSI Packaging Workshop of Japan 30 November-2 December 2004

Kyoto Research Park, Kyoto, JapanSponsored by the IEEE CPMT Society and National Institute for Standards and Technology

The VLSI Packaging Workshop of Japan is held every other year since 1992 in the best season of Kyoto, which is the ancient capital of Japan, and it has become a well known international workshop of advanced packaging technologies. The committee strongly encourages you to attend this workshop and participate in the discussion, in order to understand the technology trend and find proper target for technology development. Bring your latest research results and share with the participants who are experts from the industry and the grove of academe, and discuss with them. Anybody who tries to contribute to the human progress through electronics is welcome to this workshop. The following areas of technology are primarily of interest to the participants.

  • Advanced fine pitch packaging

  • 3D packaging and COC (Chip-on-Chip)

  • Micro bumping technology

  • Laminated materials and processing

  • RF components and modules

  • Integrated passives

  • Packaging for optoelectronics

  • Failure mechanisms and reliability improvement

  • Electrical performance and thermal management

  • Wafer level CSP

  • Manufacturing technology

  • Pb free interconnections

  • Materials for high speed application and wafer process

  • RFID tag

  • System in package

  • MEMS packaging technologies

  • Assembly and packaging challenges for Cu/low-k chips

  • Wafer level burn-in

The official language of this workshop are English. Thirty minutes allocated for each presentation, and it should include 5-10min for Q&A. Authors who give outstanding papers will receive official recommendations for paper submission to IEEE Transactions of CPMT by the Japan Chapter and the Workshop Committee. This workshop will be held at Kyoto Research Park where the 6th Workshop was held in 2002.

Commercial purpose exhibition will also be held there, as it was done at the earlier workshop to promote commercial products for packaging. Those who are trying to promote new products for packaging should not miss this opportunity. The details of the exhibition will shortly be available on the Workshop's Web site: http://homepage1.nifty.com/ ieeetokyo/chapter/cpmt/vlsip.html

Submission of abstracts

Those who wish to contribute to the workshop should send a two-page summary of their paper (including figures) to the Program Chair by 28 May 2004. The title of the paper as well as the names and affiliations of all authors must appear on the summary. If the paper is accepted, the summary shall be written to fit in a four-page format for the workshop's proceedings by 3 September 2004. Notification of the acceptance will be given by 9 July 2004.

Program ChairMichitaka Kimura, Renesas Technology Corp. 4-1, Mishear, Tami-shi, Hyogo, 664-0005, Japan. Tel: +81-72-784-7127; Fax: +81-72-780-2676; E-mail: kimura.michitaka@renesas.com

General ChairMasahiko Kohno, Dow Chemical Japan Limited. E-mail: mkohno@dow.com

Vice ChairTomoshi Ohde, Sony Computer Entertainment Inc. George Harman, NIST

Japanese CommitteeFuminori Ishitsuka, NTT ElectronicsHiroshi Manita, CasioTadaaki Mimura, Matsushita ElectronicsHirofumi Nakajima, NEC ElectronicsAtsushi Nakamura, Renesas Tech.Atsushi Okuno, Japan RecKanji Otsuka, Meisei Univ.Hiroshi Shibata, Osaka Inst. Tech.Toshio Sudo, ToshibaTakeshi Takamori, OkiHiroshi Yamada, ToshibaNoboru Iwasaki, NTTNobuo Kamehara, Fujitsu

US CommitteePhillip Garrou, Dow ChemicalSheng Liu, Wayne State Univ.Len Schaper, Univ. of ArkansasEphraim Suhir, IOLONE. Jan Vardaman, TechSearch

European CommitteeRolf Aschenbrenner, IZM, DESoeren Noerlyng, Micronsult, DenmarkDavid Whalley, Loughborough Univ. UKHarufumi Kobayashi, OkiKaoru Kobayashi, Kyocera SLC Tech.

Asian CommitteeC.P. Hung, ASE, TaiwanJung-Ihl Kim, Amkor, KoreaRicky Lee, HKUST, Hong KongThiam-Beng Lim, IME, SingaporeKyung-Wook Paik, KAIST, Korea

IEEE CPMT Japan ChapterNobuo Iwase, Toshiba

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