Keywords
Citation
(2000), "APEX tutorials to focus on SMT, advanced component packaging", Soldering & Surface Mount Technology, Vol. 12 No. 1. https://doi.org/10.1108/ssmt.2000.21912aab.013
Publisher
:Emerald Group Publishing Limited
Copyright © 2000, MCB UP Limited
APEX tutorials to focus on SMT, advanced component packaging
APEX tutorials to focus on SMT, advanced component packaging
Keywords: IPC, Electric component packaging
IPC have announced the schedule of daylong tutorials at APEXSM, IPC SMEMA Council's Electronics Assembly Process Exhibition and Conference.
Sixteen sessions are planned, addressing the spectrum of electronics assembly, from the basics of surface mount technology to advanced packaging materials. Tutorials will be held on 12 March from 8.30a.m. to 4.00p.m.
Highlights include:
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Surface mount technology: principles and practice, Ray Prasad, Prasad Consultancy Group - attendees will explore SMT design and manufacturing processes, materials and equipment, and the interdependency of design and manufacturing for higher yield, lower cost, and faster time to market.
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Advanced packaging materials and processes for BGA, flip chip, CSP, and COB, Ken Gilleo, Cookson Electronics Group - this tutorial will present all types of non-conductive adhesives and encapsulants, focusing on advanced packages. Recent developments in screen printed dams, stenciled encapsulants, and molded underfill will be included with cost/benefit comparisons.
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Chip scale and wafer level packaging technologies for semiconductors, Joe Fjelstad, Pacific Consultants, LLC - a review will be given on the basic design, construction, and performance aspects of CSPs that are now in the marketplace or under development. Emerging CSP standards, as well as innovative options in IC package design, including wafer level packaging will also be reviewed.
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Testing high density SMT circuit boards using ICT/MDA, vision, and flying probe, Robert Hanson, AmeriCom Test and SMT Technology - as the trend toward increased PCB complexity continues, there is a growing need to address testing issues earlier in the design process. Among the topics the session covers are proven concurrent engineering approaches to PC board design and layout steps that cut testing costs.
For more information on the APEX educational program, contact John Riley at (847) 790 5308, JohnRiley@ipc.org Or visit the APEX Web site at www.apex2000.org