Fujitsu Standardizes on Cadence DFM Technologies for 28 nm ASIC and mixed-signal designs

Microelectronics International

ISSN: 1356-5362

Article publication date: 20 January 2012



(2012), "Fujitsu Standardizes on Cadence DFM Technologies for 28 nm ASIC and mixed-signal designs", Microelectronics International, Vol. 29 No. 1.



Emerald Group Publishing Limited

Copyright © 2012, Emerald Group Publishing Limited

Fujitsu Standardizes on Cadence DFM Technologies for 28 nm ASIC and mixed-signal designs

Article Type: Industry news From: Microelectronics International, Volume 29, Issue 1

Fujitsu Semiconductor Limited has adopted Cadence® signoff design-for-manufacturing (DFM) technologies for its complex 28-nanometer ASIC and system-on-chip (SoC) mixed-signal designs. Deploying the Cadence DFM offerings helps Fujitsu Semiconductor engineers ensure high yield, predictability, and a faster path to Silicon Realization for next-generation chips that will serve as the brains of the company’s advanced consumer electronics. The Cadence end-to-end digital and analog flows for Silicon Realization deliver DFM in-design technology within the Virtuoso® custom/analog and Encounter® digital flows.

Following comprehensive benchmarking, Fujitsu Semiconductor selected the Cadence Litho Physical Analyzer, Cadence CMP Predictor and Cadence Litho Electrical Analyzer for 28-nanometer in-design physical signoff and variability optimization for its ASIC and SoC designs.

As process geometries shrink beyond 28 nanometres, the Cadence DFM technologies enable Fujitsu Semiconductor to tackle the essential tasks of accurately modelling and predicting the impact of physical and electrical variability (layout dependent effects) on the yield and performance of a chip. Cadence in-design DFM signoff tools enable engineers to analyze these impacts, and fix problems, during digital and custom design implementation, rather than the traditional – and more costly and risky-route of addressing DFM signoff checks after the design is completed and ready to tape out.

The Cadence Litho Physical Analyzer leverages proprietary, foundational algorithms to provide near-linear scalability, thereby providing blazing fast silicon convergence. The Cadence CMP Predictor allows Fujitsu Semiconductor engineers to detect topography variations of their manufacturing process early on via extensive simulations. Fujitsu Semiconductor design teams use the Cadence Litho Electrical Analyzer to identify and optimize their libraries for layout-dependent effect variability early on, therefore ensuring that their design meets their planned performance metrics.

Related articles